KR-102962683-B1 - Semiconductor device and method of fabricating semiconductor device

KR102962683B1KR 102962683 B1KR102962683 B1KR 102962683B1KR-102962683-B1

Abstract

The technical concept of the present invention provides a semiconductor device comprising: a semiconductor substrate; an interlayer insulating film disposed on the semiconductor substrate; a first via structure penetrating the semiconductor substrate and the interlayer insulating film and having a first diameter; and a second via structure penetrating the semiconductor substrate and having a second diameter larger than the first diameter of the first via structure at the same vertical level; wherein the sidewall of the first via structure includes at least one undercut region protruding toward the center of the first via structure, and the outer wall of the second via structure at a vertical level higher than the undercut region contacts only the semiconductor substrate and the interlayer insulating film.

Inventors

권민영
박광욱
이영민
이인영
조성동

Assignees

삼성전자주식회사

Dates

Publication Date: 20260507
Application Date: 20211208

Claims (10)

semiconductor substrate; An interlayer insulating film disposed on the semiconductor substrate; A first via structure penetrating the semiconductor substrate and the interlayer insulating film and having a first diameter; and A second via structure penetrating the semiconductor substrate and having a second diameter larger than the first diameter of the first via structure at the same vertical level; comprising The side wall of the first via structure includes at least one undercut region protruding toward the center of the first via structure, and At a vertical level higher than the above undercut region, the outer wall of the second via structure contacts only the semiconductor substrate and the interlayer insulating film, and It further includes a third via structure that penetrates the semiconductor substrate and the interlayer insulating film and has a third diameter larger than the second diameter of the second via structure at the same vertical level, The side wall of the first via structure includes at least two first undercut regions protruding inwardly into the first via structure, and A semiconductor device characterized in that the side wall of the second via structure includes at least one second undercut region protruding inwardly from the second via structure.
In Article 1, A semiconductor device characterized in that the first via structure comprises a first via insulating film extending with a substantially uniform thickness along the sidewall of a first via hole, a first barrier film extending with a substantially uniform thickness along the sidewall of the first via insulating film, and a first via plug filling an internal space defined by the first barrier film.
In Article 2, In the above undercut area, A semiconductor device characterized in that the sidewalls of each of the first via insulating film and the first barrier film protrude into the interior of the first via structure.
delete
In Article 1, A semiconductor device characterized in that the vertical level of the second undercut region is positioned between the uppermost undercut region among the plurality of first undercut regions and the lowermost undercut region among the plurality of first undercut regions.
semiconductor substrate; An interlayer insulating film provided on the semiconductor substrate; A signal via structure penetrating the semiconductor substrate and the interlayer insulating film; and A power via structure penetrating the semiconductor substrate and the interlayer insulating film; It includes, and the sidewall of the signal via structure includes at least one undercut region protruding toward the center of the signal via structure, The height of the signal via structure and the height of the power via structure are substantially the same, and The signal via structure has a first diameter, and the power via structure has a second diameter larger than the first diameter of the signal via structure at the same vertical level, At a vertical level higher than the above undercut region, the outer wall of the power via structure contacts only the semiconductor substrate and the interlayer insulating film, and It further includes an additional via structure that penetrates the semiconductor substrate and the interlayer insulating film and has a third diameter larger than the second diameter of the power via structure at the same vertical level, The side wall of the signal via structure includes at least two first undercut regions protruding inwardly into the signal via structure, and A semiconductor device characterized in that the side wall of the power via structure includes at least one second undercut region protruding inwardly from the power via structure.
A step of forming an interlayer insulating film on a semiconductor substrate; A step of forming a mask material film on the interlayer insulating film above; A step of removing a portion of a mask material film on the upper surface of each of a first location for forming a first via structure having a first diameter and a second location for forming a second via structure having a second diameter; A step of forming a first preliminary recess by partially removing the interlayer insulating film at the first position and the semiconductor substrate; A step of forming a second preliminary recess by partially removing the interlayer insulating film or the semiconductor substrate at the second position; A step of simultaneously etching portions of the semiconductor substrate at each of the first and second preliminary recesses to form a first via hole and a second via hole, respectively; A step of forming the first via structure and the second via structure, respectively, within the first via hole and the second via hole; and The method includes the step of forming external connection terminals electrically connected to the first via structure and the second via structure; The depth of the first preliminary recess is deeper than the depth of the second preliminary recess, and The diameter of the first preliminary recess is smaller than the diameter of the second preliminary recess, and A method for manufacturing a semiconductor device, wherein the step of removing a portion of the mask material film at the second position is characterized by exposing the mask material film using a reticle having a scattering bar, wherein the scattering bar is disposed on the upper surface of the second position.
In Article 7, A method for manufacturing a semiconductor device characterized in that, at a vertical level higher than the lower surface of the first pre-recess, the outer wall of the second via structure contacts only the semiconductor substrate and the interlayer insulating film.
In Article 7, The lower surface of the first pre-recess is characterized by being located at a vertical level lower than the upper surface of the semiconductor substrate, and The lower surface of the above-mentioned second preliminary recess is, Located in substantially the same plane as the upper surface of the semiconductor substrate, or, A method for manufacturing a semiconductor device characterized by being located at a vertical level lower than the upper surface of the semiconductor substrate.
In Article 7, The side wall of the first via structure includes at least one undercut region protruding toward the center of the first via structure, and A method for manufacturing a semiconductor device characterized in that at least one of the above undercut regions is the same as the position of the lower surface of the first preliminary recess.

Description

Semiconductor device and method of fabricating semiconductor device The present invention relates to a semiconductor device, a semiconductor package, and a method for manufacturing a semiconductor device, and more specifically, to a semiconductor device, a semiconductor package, and a method for manufacturing a semiconductor device that has fast data processing and low power consumption. With the active development of 3D (3-dimensional) packages that stack multiple semiconductor chips within a single semiconductor package, through-silicon-via (TSV) technology, which forms vertical electrical connections through a substrate or die, is being recognized as very important. To improve the performance of 3D packages, there is room for improvement in terms of data speed and power consumption. FIG. 1 is a planar layout diagram for explaining a semiconductor device according to embodiments of the technical concept of the present invention. Figure 2 is an enlarged view showing the first TSV unit region of Figure 1. FIG. 3 is a side view showing a cross-section cut along the line III-III' of FIG. 2 in a semiconductor device according to one embodiment of the present invention. Figures 4a and 4b are detailed enlarged views of the part indicated by IV in Figure 3. FIG. 5 is a side view showing a cross-section cut along the line III-III' of FIG. 2 in a semiconductor device according to another embodiment of the present invention. FIG. 6 is a side view showing a cross- section of a semiconductor device according to another embodiment of the present invention. FIG. 7 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 8a to 8h are cross-sectional views illustrating a method for manufacturing the semiconductor device. FIG. 9 is a flowchart illustrating in more detail the steps of forming the first and second preliminary recesses of FIG. 7. FIG. 10 is a flowchart showing in more detail the steps of forming via holes for the first via structure and via holes for the second via structure of FIG. 7. FIGS. 11a to 11d are side cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 12 is a cross-sectional view showing the configuration of a semiconductor package according to embodiments of the technical concept of the present invention. Embodiments of the present invention will be described in detail below with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. FIG. 1 is a planar layout diagram for explaining a semiconductor device (100) according to embodiments of the technical concept of the present invention. Referring to FIG. 1, a semiconductor device (100) may include a plurality of cell regions (14). A plurality of memory cells may be arranged in the plurality of cell regions (14). A plurality of word lines, a plurality of bit lines, a sense amplifier, etc. may be arranged in various ways in the plurality of cell regions (14). A peripheral region may be provided around the plurality of cell regions (14), and the peripheral region may include a plurality of column decoders (16), a plurality of row decoders (18), and a TSV (through-silicon via) region (20). The plurality of column decoders (16) may receive an address and decode it to select a column line of the cell region (14). The plurality of row decoders (18) may receive an address and decode it to output a row address for selecting a row line of the cell region (14). The memory semiconductor chip (12) may further include a light driver, an input/output sense amplifier, and an input/output buffer. A TSV region (20) may be located in the approximate center of the memory semiconductor chip (12). A plurality of TSV structures (30) may be arranged in the TSV region (20). The number and shape of the plurality of TSV structures (30) exemplified in FIG. 1 are merely examples, and the technical concept of the present invention is not limited to what is exemplified in FIG. 1. For example, about several hundred to several thousand TSV structures (30) may be arranged in the TSV region (20). The input/output buffer included in the memory semiconductor chip (12) can receive a signal from the outside through the TSV structure (30) or transmit a signal to the outside through the TSV structure (30). The above TSV region (20) may include a plurality of first to fourth TSV unit regions (22, 24, 26, 28). The plurality of first to fourth TSV unit regions (22, 24, 26, 28) may include a first TSV unit region (22), a second TSV unit region (24), a third TSV unit region (26), and a fourth TSV unit region (28). Although FIG. 1 illustrates that the TSV region (20) includes four first to fourth TSV unit regions (22, 24, 26, 28), the technical concept of the present invention is not limited to what is illustrated in FI