KR-102962684-B1 - Nonvolatile memory device including multi-stack memory block and method for operating thereof

KR102962684B1KR 102962684 B1KR102962684 B1KR 102962684B1KR-102962684-B1

Abstract

A method of operation of a memory system comprising a memory controller and a non-volatile memory device that operates based on the control of the memory controller according to one aspect of the technical concept of the present disclosure and includes a first memory block and a second memory block, comprises the steps of: determining whether the first memory block satisfies a block reset condition; applying a turn-on voltage to the word lines of dummy cells constituting the first memory block when the first memory block satisfies the block reset condition; transferring data previously programmed in the first memory block to the second memory block; erasing the first memory block; and reprogramming the dummy cells of the first memory block.

Inventors

이요한
유재덕
조지호

Assignees

삼성전자주식회사

Dates

Publication Date: 20260508
Application Date: 20220330
Priority Date: 20211110

Claims (10)

A method of operation of a memory system comprising a memory controller and a non-volatile memory device that operates based on the control of the memory controller and includes a first memory block and a second memory block, wherein A step in which the memory controller determines whether the first memory block satisfies a block reset condition; A step of applying a turn-on voltage to the word lines of dummy cells constituting the first memory block when the first memory block satisfies the block reset condition; A step of transferring data already programmed in the first memory block to the second memory block; A step of erasing the first memory block; and The method includes the step of reprogramming the dummy cells of the first memory block. The step of the memory controller determining whether the first memory block satisfies the block reset condition is The memory controller compares the voltage level of the threshold voltage of the dummy cells constituting the first memory block with the voltage level of the first reference voltage; and The memory controller includes the step of determining that the block reset condition is satisfied when the voltage level of the threshold voltage of the dummy cells constituting the first memory block is lower than 0 or higher than the voltage level of the first reference voltage, and A method of operating a memory system characterized in that the voltage level of the first reference voltage is a threshold value at which the first memory block can normally perform a read operation.
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In paragraph 1, The voltage level of the first reference voltage above is, A method of operation of a memory system characterized by the threshold voltage of a memory cell constituting the first memory block being equal to the maximum voltage level that can be.
A method of operating a non-volatile memory device comprising first to third memory blocks, wherein each of the first to third memory blocks comprises a first sub-block comprising a plurality of memory cells, a second sub-block comprising a plurality of memory cells and disposed above the first sub-block, and a dummy block comprising a plurality of dummy cells and disposed between the first sub-block and the second sub-block. A step of receiving a command that commands the operation of the first memory block; When the first memory block does not satisfy the block reset condition, the first memory block performs an operation based on the command; and The method includes the step of performing a block reset operation when the first memory block satisfies a block reset condition, and The step of performing the above block reset operation is, A step of applying a turn-on voltage to dummy word lines included in the dummy block of the first memory block; A step of transferring data already programmed in the first sub-block or the second sub-block of the first memory block to the second memory block; A step of performing an erase operation on the entire first memory block; and The method includes the step of reprogramming the dummy cells of the first memory block. The above block reset condition is, Satisfied when the voltage level of the threshold voltage of the dummy cells of the first memory block is lower than 0 or higher than the voltage level of the first reference voltage, and A method of operation of a non-volatile memory device characterized in that the voltage level of the first reference voltage is a threshold value at which the first memory block can normally perform a read operation.
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In paragraph 4, The above command is, It is an erase command for the first sub-block or the second sub-block, which is the sub-block to be erased of the first memory block, and When the first memory block does not satisfy the block reset condition, the step of the first memory block performing an operation based on the command is A method of operating a non-volatile memory device characterized by including the step of applying a voltage to the dummy word lines of the first memory block to prevent injecting holes into the second sub-block, which is a non-erasable sub-block of the first memory block, or into the first sub-block.
In paragraph 4, The second sub-block of the first memory block is a sub-block in which data has already been programmed, and The above command is a program command for the first sub-block of the first memory block, and When the first memory block does not satisfy the block reset condition, the step of the first memory block performing an operation based on the command is The method further includes the step of applying a block pass voltage to the word lines included in the second sub-block of the first memory block and the dummy word lines of the first memory block. A method of operation of a non-volatile memory device characterized in that the voltage level of the block pass voltage is the same as the voltage level of the turn-on voltage.
In paragraph 4, The first sub-block of the first memory block is a sub-block in which data has already been programmed, and The above command is a program command for the second sub-block of the first memory block, and A step of applying a turn-off voltage to the dummy word lines of the first memory block when the first memory block satisfies a dummy block turn-off condition; and A method of operating a non-volatile memory device characterized by further including a step of determining whether the first memory block satisfies the block reset condition when the first memory block does not satisfy the dummy block turn-off condition.
In paragraph 8, The above dummy block turn-off condition is, Satisfied when the voltage level of the threshold voltage of the dummy cells of the first memory block is lower than 0 or higher than the voltage level of the second reference voltage, and A method of operation of a non-volatile memory device characterized in that the voltage level of the second reference voltage is a threshold value at which the dummy cells of the first memory block can electrically block the first sub-block of the first memory block and the second sub-block of the first memory block.
In paragraph 8, When the first memory block does not satisfy a block reset condition, the method further includes the step of applying a turn-on voltage to the dummy word lines of the first memory block before the first memory block performs an operation based on the command. When the first memory block satisfies the block reset condition, the method further includes the step of programming the data intended to be programmed in the second sub-block of the first memory block into the second memory block before the first memory block performs the block reset operation. The step of transferring data already programmed in the first memory block to the second memory block is A method of operating a non-volatile memory device characterized by including the step of transferring data already programmed in the first sub-block of the first memory block to an unprogrammed sub-block of the second memory block or the third memory block.

Description

Nonvolatile memory device including multi-stack memory block and method for operating thereof The technical concept of the present disclosure relates to a non-volatile memory device including a multi-stack memory block and a method of operating the same, and more specifically, to a non-volatile memory device and a method of operating the same that monitors the threshold voltage of dummy word lines and maintains the threshold voltage of dummy word lines constant by performing a block reset operation. Systems using semiconductor chips use Dynamic Random Access Memory (DRAM) as operational memory or main memory to store data or instructions used by a host or to perform computational operations, and use storage devices including non-volatile memory as storage media. As storage devices with large capacities are required, the number of memory cells and word lines stacked on the substrate of non-volatile memory is increasing, and recently, research on non-volatile memory devices that stack memory cells in a three-dimensional structure, such as 3D NAND flash memory devices, is actively underway to improve the storage capacity and density of memory. FIG. 1 is a flowchart illustrating a block reset method for a non-volatile memory device according to exemplary embodiments of the present invention. FIG. 2 is a block diagram conceptually illustrating a memory system according to exemplary embodiments of the present invention. FIG. 3 is a block diagram showing a non-volatile memory device according to exemplary embodiments of the present invention. FIG. 4 is a perspective view showing a memory block (BLK1) according to exemplary embodiments of the present invention. FIG. 5 is an equivalent circuit diagram of a non-volatile memory device according to exemplary embodiments of the present invention. FIG. 6 is a flowchart illustrating a method for erasing a non-volatile memory device according to exemplary embodiments of the present invention. FIG. 7 is a flowchart illustrating a programming method for a non-volatile memory device according to exemplary embodiments of the present invention. FIG. 8 is a flowchart illustrating a programming method for a non-volatile memory device according to exemplary embodiments of the present invention. FIG. 9 is a diagram illustrating the threshold voltage dispersion of memory cells programmed according to exemplary embodiments of the present invention. FIG. 10 is a flowchart illustrating a method for recovering data from a non-volatile memory device when a readout error occurs according to exemplary embodiments of the present invention. FIG. 11 is a cross-sectional view showing the structure of a non-volatile memory device according to exemplary embodiments of the present invention. FIG. 12 is a block diagram showing a computing system according to exemplary embodiments of the present invention. FIG. 13 is a block diagram showing an SSD system according to exemplary embodiments of the present invention. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. When describing with reference to drawings, identical or corresponding components are assigned the same reference numerals, and redundant descriptions thereof are omitted. FIG. 1 is a flowchart illustrating a block reset method for a non-volatile memory device according to exemplary embodiments of the present invention. Referring to FIG. 1, a block reset method (S100) of a non-volatile memory device may include a plurality of steps (S110 to S150). A plurality of cell strings may be divided into two sub-blocks or into three or more sub-blocks, as described below with reference to FIG. 5. A plurality of cell strings may include dummy blocks placed between the sub-blocks, as described below with reference to FIG. 5. In step (S110), it can be determined whether the block reset condition is satisfied for the first memory block (BLK1 in FIG. 3). To determine whether the block reset condition is satisfied, the threshold voltage (Vth, DC ) of the dummy cells included in the dummy block (DB in FIG. 4 and 5) can be monitored. The threshold voltage (Vth, DC ) of the dummy cells can be compared with the first reference voltage (V1). When the voltage level of the threshold voltage (Vth, DC ) of the dummy cells is higher than the voltage level of the first reference voltage (V1), an error may occur during the read operation. That is, the voltage level of the first reference voltage (V1) may be a threshold value at which the first memory block (BLK1 in FIG. 3) can normally perform the read operation. Accordingly, the voltage level of the first reference voltage (V1) may be a reference value for determining whether a block reset operation is necessary. The voltage level of the first reference voltage (V1) may be a preset value or a value entered by a user. The voltage level of the first reference voltage (V1) will be explained in more detail with reference to FIG. 9, which will be descr