KR-102962685-B1 - Memory device having row decoder array architecture

Abstract

A memory device having a row decoder array architecture is disclosed. The memory device includes a peripheral circuit structure and a cell array structure that overlaps the peripheral circuit structure in a vertical direction. The cell array structure includes a plurality of memory blocks divided into a normal cell area and a dummy cell area, and the dummy cell area includes a bitline penetration electrode area. The peripheral circuit structure includes a row decoder area in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and at least one bitline penetration electrode area is disposed corresponding to the block height of the unit row decoder circuit.

Inventors

• 김승연
• 박주용
• 전홍수

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20220318

Priority Date

20211110

Claims (10)

1. Peripheral circuit structures; and It includes a cell array structure that overlaps vertically with the peripheral circuit structure on the above peripheral circuit structure, The cell array structure comprises a memory cell region including a plurality of word lines extending in a first horizontal direction and a plurality of bit lines extending in a second horizontal direction intersecting the first horizontal direction, and the memory cell region comprises a plurality of memory blocks whose block height is determined by a plurality of word line cut regions extending along the first horizontal direction, and the plurality of memory blocks are divided into a normal cell region and a dummy cell region, and the dummy cell region comprises a bit line penetrating electrode region including penetrating electrodes connected to the plurality of bit lines and penetrating the plurality of word lines to extend vertically into the interior of the peripheral circuit structure. The above peripheral circuit structure includes a row decoder region that controls the plurality of word lines of each of the memory blocks of the above normal cell region, and The row decoder region is arranged corresponding to the plurality of memory blocks, and a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arrayed, and A memory device comprising at least one bitline penetration electrode region in the plurality of memory blocks arranged to match the block height of the unit row decoder circuit.
2. In paragraph 1, The bitline penetration electrode region includes a region corresponding to m (m is a positive integer) of the plurality of memory blocks, and A memory device in which a bitline penetration electrode area of m block height is placed to match the block height of arranged unit row decoder circuits.
3. In paragraph 1, The memory cell area is divided into a plurality of tiles by a tile cut area that extends along the first horizontal direction, and The above dummy cell region further includes a memory block adjacent to the tile cut region among the plurality of memory blocks, and A memory device comprising at least one memory block adjacent to the tile cut area among the plurality of memory blocks arranged to match the block height of the unit row decoder circuit.
4. In paragraph 1, The above dummy cell region is a memory device that further includes edge memory blocks on both sides of the memory cell region in the second horizontal direction among the plurality of memory blocks.
5. In paragraph 4, A memory device comprising at least one edge memory block among the plurality of memory blocks arranged to match the block height of the unit row decoder circuit.
6. In paragraph 4, A memory device comprising m (m is a positive integer) memory blocks adjacent to the edge memory block, wherein the plurality of memory blocks arranged to match the block height of the arranged unit row decoder circuits.
7. In paragraph 1, A memory device in which the n memory blocks shared by the above unit row decoder circuit are arranged adjacent to each other.
8. In paragraph 1, A memory device in which the n memory blocks shared by the unit row decoder circuit are spaced apart from each other.
9. Peripheral circuit structures; and It includes a cell array structure that overlaps vertically with the peripheral circuit structure on top of the peripheral circuit structure, The cell array structure comprises a memory cell region including a plurality of word lines extending in a first horizontal direction and a plurality of bit lines extending in a second horizontal direction intersecting the first horizontal direction, and dummy step regions disposed on both sides of the memory cell region, wherein the memory cell region comprises a plurality of memory blocks whose block height is determined by a plurality of word line cut regions extending along the first horizontal direction, and the plurality of memory blocks are divided into a normal cell region and a dummy cell region, and in the dummy step region, the plurality of word lines extend mutually parallel to each other in the first horizontal direction and the second horizontal direction and overlap each other in the vertical direction. The above peripheral circuit structure includes a row decoder region that controls the plurality of word lines of each of the memory blocks of the above normal cell region, and The row decoder region is arranged corresponding to the plurality of memory blocks, and a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and A memory device in which at least one dummy step area is placed to match the block height of the above unit row decoder circuit.
10. In Paragraph 9, The memory cell area is divided into a plurality of tiles by a tile cut area that extends along the first horizontal direction, and The above dummy cell region further includes a memory block adjacent to the tile cut region among the plurality of memory blocks, and A memory device comprising at least one memory block adjacent to the tile cut area among the plurality of memory blocks arranged to match the block height of the unit row decoder circuit.

Description

Memory device having row decoder array architecture The present invention relates to semiconductor memory devices, and more specifically, to a memory device having a row decoder array architecture. Recently, with the increasing multifunctionality of information and communication devices, there is a demand for larger capacity and higher integration of memory devices. As memory cell sizes are reduced for high integration, the operating circuits and/or wiring structures included in memory devices for operation and electrical connection are also becoming more complex. Accordingly, there is a demand for memory devices that have excellent electrical characteristics while improving the integration density of memory devices. To improve the storage capacity and integration density of memory devices, non-volatile memory devices that stack memory cells in a three-dimensional structure, such as 3D NAND flash memory, are being researched. The architecture of a non-volatile memory device is disclosed in Korean Registered Patent No. 10-1759807. In 3D NAND flash memory, the number of word lines stacked vertically on the substrate may increase in accordance with the trend of increasing the capacity of memory blocks. At this time, row decoders connected to the word lines may be positioned to correspond to the height of the memory block determined by a plurality of word line cut areas (WLC, FIG. 5). Accordingly, the height of the row decoders may be the same as the height of the memory blocks. At this time, memory blocks may be added to match the height of the row decoders, which may result in a problem of increasing the chip size. FIG. 1 is a drawing illustrating a memory device according to exemplary embodiments of the present invention. FIG. 2 schematically shows the structure of a memory device according to one embodiment of the present disclosure. FIG. 3 is an equivalent circuit diagram of a memory cell array according to embodiments of the present invention. FIG. 4 is a perspective view showing a memory block according to an embodiment of the present invention. FIG. 5 is a schematic plan view of a memory device according to embodiments of the present invention. FIG. 6 is a diagram illustrating a row decoder of a 2 memory block sharing scheme according to an embodiment of the present invention. FIGS. 7a through 7c show examples of row decoder array architectures of the 2 memory block sharing scheme of FIG. 6. FIGS. 8A to 8F show row decoder array architectures according to embodiments of the present invention. FIGS. 9 and FIGS. 10A through 10F show other examples of row decoder array architectures of the 2 memory block sharing scheme of FIG. 6. FIG. 11 is a diagram illustrating a row decoder of a 4-memory block sharing scheme according to one embodiment of the present invention. FIGS. 12a to 12c, FIGS. 13A to 13J, FIGS. 14A to 14G, FIGS. 15A to 15F, FIGS. 16A to 16E and FIGS. 17A to 17E show examples of row decoder array architectures of the 4 memory block sharing scheme of FIG. 11. FIGS. 18, FIGS. 19A to 19J, FIGS. 20A to 20G, FIGS. 21A to 21F, FIGS. 22A to 22E and FIGS. 23A to 23G show other examples of row decoder array architectures of the 4 memory block sharing scheme of FIG. 11. FIG. 24 is a cross-sectional view showing a memory device according to one embodiment of the present invention. FIG. 25 is a cross-sectional view showing a memory device according to another embodiment of the present invention. FIG. 26 is a block diagram showing an example of applying a memory device according to some embodiments of the present invention to an SSD system. FIG. 1 is a diagram illustrating a memory device (10) according to exemplary embodiments of the present invention. Referring to FIG. 1, the memory device (10) may include a memory cell array (100) and a peripheral circuit (200), and the peripheral circuit (200) may include a row decoder (220), a control logic circuit (230), and a page buffer (240). Although not illustrated, the peripheral circuit (200) may further include a voltage generator, a data input/output circuit, an input/output interface, a temperature sensor, a command decoder, etc. In embodiments of the present disclosure, the memory device (10) may be a non-volatile memory device, and hereinafter, "memory device" refers to a non-volatile memory device. A memory cell array (100) can be connected to a row decoder (220) via word lines (WL), string select lines (SSL), and ground select lines (GSL), and can be connected to a page buffer (240) via bit lines (BL). In the memory cell array (100), a plurality of memory cells included in a plurality of memory blocks (BLK1, BLK2, ..., BLKn) may be flash memory cells. Hereinafter, embodiments of the present disclosure will be described in detail with the example that the plurality of memory cells are NAND flash memory cells. However, the present invention is not limited thereto, and in some embodiments, the plurality of memory cells may be resistive memory cells such as Re