KR-102962779-B1 - PLASMA ETCHING CHEMISTRIES OF HIGH ASPECT RATIO FEATURES IN DIELECTRICS

Abstract

A method for etching features into a stack under a patterned mask in an etching chamber is provided. The stack is cooled with a coolant having a coolant temperature of -20°C or lower. An etching gas flows into the etching chamber. Plasma is generated from the etching gas. Features are selectively etched into the stack against the patterned mask.

Inventors

• 카나릭, 케렌 제이.
• 탄, 사만다 시암-화
• 판, 양
• 막스, 제프리

Assignees

• 램 리써치 코포레이션

Dates

Publication Date

20260508

Application Date

20190312

Priority Date

20180316

Claims (20)

1. a) a step of supporting a substrate on a chuck within a chamber of a plasma processing system, wherein the substrate comprises a silicon-containing film and the chuck has a lower electrode; b) A step of cooling the substrate to a temperature of -20 ℃ or lower; c) a step of providing a halogen-containing gas; d) a step of providing pentafluoride gas; and e) a step of generating a plasma from the halogen-containing gas and the pentafluoride gas, wherein the plasma is a plasma for etching features within the silicon-containing film and depositing sidewall passivation on the sidewalls of the features, the etching method comprising the step of generating the plasma.
2. In Article 1, An etching method comprising, after step e) above, an additional step of providing a bias.
3. In Article 1, An etching method comprising the step of generating the plasma from the halogen-containing gas and the pentafluoride gas, wherein the step of providing RF power.
4. In Article 1, The above pentafluoride gas is an etching method comprising phosphorus pentafluoride ( PF₅ ).
5. In Article 1, The above halogen-containing gas is an etching method comprising a free fluorine-providing component.
6. In Article 1, An etching method comprising, prior to step e) above, a step of providing one or more of a hydrogen-containing component, a hydrocarbon-containing component, a fluorocarbon-containing component, and an iodine-containing component.
7. delete
8. In Article 1, An etching method comprising, prior to step e) above, a step of providing oxygen gas.
9. In Article 1, An etching method comprising, after step e) above, further a step of providing a bias having a magnitude of at least 400 V.
10. In Article 1, An etching method wherein the silicon-containing film comprises at least two different silicon-containing layers.
11. In Article 10, An etching method wherein the above at least two different silicon-containing layers comprise a silicon oxide layer and a silicon nitride layer.
12. In Article 10, An etching method wherein the above at least two different silicon-containing layers comprise a silicon oxide layer and a polysilicon layer.
13. In Article 10, An etching method wherein the substrate further comprises a mask on the at least two different silicon-containing layers.
14. a) a step of supporting a substrate on a chuck within a chamber of a plasma processing system, wherein the substrate comprises a silicon-containing film and the chuck has a lower electrode; b) a step of providing a halogen-containing gas; c) a step of providing pentafluoride gas; and d) a step of providing RF power to generate a plasma from the halogen-containing gas and the pentafluoride gas, wherein the plasma is a plasma for etching features within the silicon-containing film and depositing sidewall passivation on the sidewalls of the features, the etching method comprising the step of providing RF power.
15. In Article 14, An etching method comprising, after step d) above, an additional step of providing a bias.
16. In Article 14, The above pentafluoride gas is an etching method comprising phosphorus pentafluoride ( PF₅ ).
17. In Article 14, An etching method further comprising the step of cooling the substrate to a temperature of -20 ℃ or lower.
18. In Article 14, The above halogen-containing gas is an etching method comprising a free fluorine-providing component.
19. In Article 14, An etching method comprising, prior to step d) above, a step of providing one or more of a hydrogen-containing component, a hydrocarbon-containing component, a fluorocarbon-containing component, and an iodine-containing component.
20. delete

Description

Plasma Etching Chemistries of High Aspect Ratio Features in Dielectrics Cross-reference regarding related applications This application claims the benefit of U.S. Provisional Patent Application No. 62/644,095 filed on March 16, 2018, which is incorporated herein by reference for all purposes. The present disclosure relates to a method for forming semiconductor devices on a semiconductor wafer. For example, in the formation of semiconductor devices, etching layers may be etched to form memory holes or lines or other semiconductor features. Some semiconductor devices may be formed, for example, by etching a single stack of silicon dioxide ( SiO2 ) to form a capacitor in a Dynamic Access Random Memory (DRAM). Other semiconductor devices may be formed by etching stacks of alternating silicon dioxide (oxide) and silicon nitride (nitride) (ONON) bilayers, or alternating silicon dioxide and polysilicon bilayers. These stacks may be used in memory applications and three-dimensional “not and” (3D NAND) gates. The background description provided herein is intended to generally provide context for the present disclosure. These stacks tend to require relatively High Aspect Ratio (HAR) etching of dielectrics. For high aspect ratio etchings, examples of the targeted etching characteristics are high etching selectivity on the mask (e.g., amorphous carbon mask), low sidewall etching with straight profiles, and a high etching rate at the etching front. The work of the inventors named herein to the extent described in this background section, as well as aspects of the present technology that may not otherwise be recognized as prior art at the time of filing, are not explicitly or implicitly acknowledged as prior art to this disclosure. In accordance with the purpose of the present disclosure and to achieve the foregoing, a method for etching features into a stack under a patterned mask in an etching chamber is provided. The stack is cooled with a coolant having a coolant temperature of -20°C or lower. An etching gas flows into the etching chamber. A plasma is generated from the etching gas. Features are selectively etched into the stack against the patterned mask. These and other features of the present disclosure will be described in more detail below in the detailed description and together with the drawings below. The present disclosure is illustrated by example, not by limitation, in the drawings of the attached drawings, where similar reference numbers refer to similar elements. Figure 1 is a high-level flowchart of one embodiment. FIG. 2 is a schematic diagram of an etching chamber that may be used in one embodiment. FIG. 3 is a schematic diagram of a computer system that may be used in the implementation of one embodiment. FIGS. 4a and FIGS. 4b are schematic cross-sectional views of a stack processed according to one embodiment. The present disclosure will now be described in detail with reference to some preferred embodiments of the disclosure as illustrated in the accompanying drawings. In the description below, numerous specific details are provided to provide a complete understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other examples, known process steps and/or structures have not been described in detail so as not to unnecessarily obscure the present disclosure. FIG. 1 is a high-level flowchart of one embodiment. In this embodiment, a stack is placed within an etching chamber (step (104)). The stack is placed under a patterned mask. The stack has at least one dielectric layer. The stack is cooled by a coolant at a cryogenic temperature (step (108)). An etching gas is provided by flowing the etching gas into the etching chamber (step (112)). The etching gas is formed into an etching plasma (step (116)). The stack is exposed to the plasma (step (120)). A bias is provided to accelerate ions from the plasma to the stack (step (124)). The stack is selectively etched against the patterned mask by the etching plasma (step (128)). The stack is removed from the etching chamber (step (132)). Etching high aspect ratio structures is also generally required using semiconductor materials such as silicon dioxide to fabricate semiconductor devices. Etching high aspect ratios requires directional (anisotropic) etching, which is distinct from isotropic etching. Generally, directional etching is achieved using ions within a plasma that are accelerated perpendicularly to the wafer surface. For example, applying a bias of 10 to 5000 eV will accelerate ions present in the plasma toward the wafer surface. The ions provide plasma etching. In specifications and claims, the word "cryogenic" refers to "cold" substrate temperatures. In conventional etching, the word "cold" refers to temperatures below -20°C. The history of cryogenic etching dates back to 1988, and it has been most extensively studied