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KR-102962843-B1 - METHOD OF DETERMINING A BUDGET COMPONENT FOR ANALYSIS OF EDGE PLACEMENT ERROR IN SEMICONDUCTOR MANUFACTURING PROCESS AND MANUFACTURING PROCESS ANALYZING DEVICE USING THE SAME

KR102962843B1KR 102962843 B1KR102962843 B1KR 102962843B1KR-102962843-B1

Abstract

The present invention relates to a method for determining a budget component for analyzing an Edge Placement Error (EPE) in a semiconductor manufacturing process, wherein (a) when metrology data is obtained for a semiconductor substrate on which at least one semiconductor manufacturing process is performed, a manufacturing process analysis device refers to the metrology data and selects at least one i-th gauge primitive based on at least one i-th critical pattern site—where i is an integer greater than or equal to 1 and less than or equal to n—of n critical pattern sites selected on the semiconductor substrate—where n is an integer greater than or equal to 1, wherein the critical pattern sites are fine pattern regions that affect the performance and yield of the semiconductor device, and i is an integer greater than or equal to 1, wherein the i_1 component to the i_m component used for EPE analysis is generated using the at least one i-th gauge primitive, wherein m is an integer greater than or equal to 1, and the i_1 EPE is obtained by combining the i_1 component to the i_m component by referring to a preset combination condition. (b) a step of generating a formulation to the i_k EPE formulation — wherein k is an integer greater than or equal to 1, and a specific component among the i_1 component to the i_m component may overlap with at least two EPE formulations among the i_1 EPE formulation to the i_k EPE formulation; (b) a step in which the manufacturing process analysis device matches each of the i_1 EPE formulation to the i_k EPE formulation to at least one target performance metric to calculate the correlations between each of the i_1 EPE formulation to the i_k EPE formulation and the at least one target performance metric, and selects the i_1 specific EPE formulation to the i_j specific EPE formulation — wherein j is an integer greater than or equal to 1 and less than or equal to k — by referring to the calculated correlations; and (c) the manufacturing process analysis device, by redistributing each of the i_1 specific budgets of i_1 specific components included in each of the i_1 specific EPE formulation to the i_j specific EPE formulation, by referencing each of the i_1 specific correlation degree corresponding to the i_1 specific EPE formulation to the i_j specific correlation degree corresponding to the i_j specific EPE formulation, thereby generating an i_1 priority for the i_1 specific components to an i_j priority for the i_j specific components, and using each of the i_1 priority to the i_j priority to determine a budget component for analyzing the EPE for the semiconductor manufacturing process or providing budget component determination information necessary for determining the budget component; the method and the manufacturing process analysis device using the same.

Inventors

  • 지태권
  • 정지훈

Assignees

  • 주식회사 세미에이아이

Dates

Publication Date
20260511
Application Date
20260407

Claims (20)

  1. A method for determining a budget component for analyzing Edge Placement Error (EPE) in a semiconductor manufacturing process, (a) When metrology data is obtained for a semiconductor substrate on which at least one semiconductor manufacturing process has been performed, a manufacturing process analysis device refers to the metrology data and selects at least one i-th gauge primitive based on at least one i-th device pattern information in n selected critical pattern sites on the semiconductor substrate—wherein n is an integer greater than or equal to 1—wherein the critical pattern sites are fine pattern regions that affect the performance and yield of the semiconductor device—wherein i is an integer greater than or equal to 1 and less than or equal to n; generates an i_1 to i_m component used for EPE analysis using the at least one i-th gauge primitive—wherein m is an integer greater than or equal to 1—and combines the i_1 to i_m component by referring to a preset combination condition to produce an i_1 EPE formulation to an i_k EPE formulation—wherein k is an integer greater than or equal to 1, and among the i_1 to i_m component A specific component may overlap with at least two of the above i_1 EPE formulations to the above i_k EPE formulations - a step of generating; (b) the manufacturing process analysis device matches each of the i_1 EPE formulations to the i_k EPE formulations to at least one target performance metric to calculate the correlations between each of the i_1 EPE formulations to the i_k EPE formulations and the at least one target performance metric, and selects the i_1 specific EPE formulation to the i_j specific EPE formulation—where j is an integer greater than or equal to 1 and less than or equal to k—by referring to the calculated correlations; and (c) The manufacturing process analysis device generates an i_1 priority for the i_1 specific components and an i_j priority for the i_j specific components by redistributing each of the i_1 specific components included in each of the i_1 specific EPE formulations and i_j specific EPE formulations by referencing each of the i_1 specific correlation corresponding to the i_1 specific EPE formulation and i_j specific correlation corresponding to the i_j specific EPE formulation, and using each of the i_1 priority to i_j priority to determine a budget component for analyzing the EPE for the semiconductor manufacturing process or providing budget component determination information necessary for determining the budget component; A method including
  2. In paragraph 1, In step (a) above, The above metrology data includes a 2D metrology image, and A method for the above manufacturing process analysis device to identify i-th element patterns located in an i-th site image corresponding to an i-th critical pattern site in a 2D metrology image through Vision AI (Artificial Intelligence), to select at least one i-th gauge primitive by referring to relationship information between the identified i-th element patterns, and to generate the i-th_1 component to the i-th_m component using the at least one i-th gauge primitive.
  3. In paragraph 1, In step (a) above, The above metrology data includes a 2D metrology image, and A method for the manufacturing process analysis device, wherein, through Vision AI, an i-th attention map or i-th vulnerability scoring map is generated for i-th element patterns located in an i-th site image corresponding to an i-th critical pattern site in a 2D metrology image, i-th candidate gauge primitives are generated by referencing the i-th attention map or the i-th vulnerability scoring map, at least one i-th gauge primitive is selected from among the i-th candidate gauge primitives by referencing spatial range conditions set for the i-th element patterns, and i-th_1 to i-m components including an i-th 3D recognition proxy component for the i-th element patterns are generated using the at least one i-th gauge primitive.
  4. In paragraph 3, A method in which the i-th 3D recognition proxy component comprises at least some of Top-CD (Critical Dimension), Bottom-CD, Sidewall asymmetry information, edge asymmetry information, and profile risk indicators corresponding to the i-th specific element pattern among the i-th element patterns.
  5. In paragraph 1, In step (a) above, A method for the above manufacturing process analysis device to determine k failure mechanisms or k ontologies corresponding to the i-th critical pattern site by referring to at least one of a failure mechanism template in which failure modes of a semiconductor device are defined and an ontology template in which ontology according to correlations between semiconductor manufacturing processes is defined, through a component combination AI, and to generate the i-th EPE formulation to the i-th EPE formulation by combining the i-th component to the i-m component based on the determined k failure mechanisms or k ontologies.
  6. In paragraph 1, In step (b) above, The above manufacturing process analysis device is a method for matching each of the i_1 EPE formulations to the i_k EPE formulations to the at least one target performance metric through an inversion model—the inversion model is a model that estimates the yield or performance of the semiconductor substrate using the EPE—calculating the i_1 correlation between the i_1 EPE formulation and the at least one target performance metric to the i_k correlation between the i_1 EPE formulation and the at least one target performance metric, and selecting each of the i_1 specific EPE formulations to the i_j specific EPE formulations among the i_1 EPE formulations to the i_k EPE formulations according to a correlation ranking determined by referring to the i_1 correlation to the i_k correlation.
  7. In paragraph 6, The above-described inverse model generates each of the i_1 EPE maps to i_k EPE maps corresponding to each of the i_1 EPE formulations to i_k EPE formulations, and calculates the i_1 to i_k correlations, which are the correlations, by matching each of the i_1 EPE maps to i_k EPE maps with a yield map or performance map representing the yield or performance in the semiconductor substrate based on at least one target performance metric.
  8. In paragraph 6, The above at least one target performance metric is a method in which the at least one target performance metric is a yield map or performance map for at least one level among a single layer level, a layer pair level, a die level, and a device level in the semiconductor substrate.
  9. In paragraph 1, In step (b) above, A method for selecting the i_1 specific EPE formulation to the i_j specific EPE formulation from at least some of the regenerated i_1 EPE formulations when the correlations of the i_1 EPE formulation to the i_k EPE formulation are less than a preset threshold correlation.
  10. In Paragraph 9, The above manufacturing process analysis device is a method for regenerating the i_1' EPE formulation to the i_k' EPE formulation through at least one sub-process among (i) a sub-process for adjusting at least some of the selection conditions for at least one i-gauge primitive, (ii) a sub-process for adjusting at least some of the generation conditions for the i_1 component to the i_m component, and (iii) a sub-process for adjusting at least some of the combination conditions for combining the i_1 component to the i_m component, by referring to the misfit diagnosis result.
  11. In a manufacturing process analysis device for determining a budget component for analyzing an edge placement error (EPE) in a semiconductor manufacturing process, A memory storing instructions for determining a budget component for analyzing edge placement errors in a semiconductor manufacturing process; and A processor for determining the budget component for analyzing the edge placement error in the semiconductor manufacturing process according to the instructions stored in the memory; Includes, The processor comprises: (I) when metrology data is obtained for a semiconductor substrate on which at least one semiconductor manufacturing process has been performed, referencing the metrology data to select at least one i-th gauge primitive based on at least one i-th critical pattern site—where i is an integer greater than or equal to 1 and n is an integer less than or equal to n—selected from the semiconductor substrate—where n is an integer greater than or equal to 1, where n is a critical pattern site—where the critical pattern site is a fine pattern region that affects the performance and yield of the semiconductor device—where i is an integer greater than or equal to 1, and using the at least one i-th gauge primitive to generate an i_1 to i_m component used for EPE analysis—where m is an integer greater than or equal to 1—and by combining the i_1 to i_m component by referring to a preset combination condition to generate an i_1 EPE formulation to an i_k EPE formulation—where k is an integer greater than or equal to 1, and a specific among the i_1 to i_m component A process for generating a component that may overlap with at least two of the i_1 EPE formulations to the i_k EPE formulations, (II) a process for matching each of the i_1 EPE formulations to the i_k EPE formulations to at least one target performance metric to calculate the correlations between each of the i_1 EPE formulations to the i_k EPE formulations and the at least one target performance metric, and selecting the i_1 specific EPE formulation to the i_j specific EPE formulation—where j is an integer greater than or equal to 1 and less than or equal to k—by referring to the calculated correlations, and (III) each of the i_1 specific budgets of the i_1 specific components included in each of the i_1 specific EPE formulation to the i_j specific EPE formulation, and the i_1 specific correlation corresponding to the i_1 specific EPE formulation A manufacturing process analysis device that performs a process of generating an i_1 priority for the i_1 specific components to an i_j priority for the i_j specific components by redistributing by referencing each of the i_j specific associations corresponding to the i_j specific EPE formulation, and using each of the i_1 priority to the i_j priority to determine a budget component for analyzing the EPE for the semiconductor manufacturing process or providing budget component determination information necessary for determining the budget component.
  12. In Paragraph 11, The above processor is, A manufacturing process analysis apparatus that, in the above process (I), the metrology data includes a 2D metrology image, identifies i-th element patterns located in an i-th site image corresponding to an i-th critical pattern site in the 2D metrology image through Vision AI (Artificial Intelligence), selects at least one i-th gauge primitive by referring to relationship information between the identified i-th element patterns, and generates the i_1 component to the i_m component using the at least one i-th gauge primitive.
  13. In Paragraph 11, The above processor is, A manufacturing process analysis apparatus that, in the above process (I), the metrology data includes a 2D metrology image, and through vision AI, generates an i-th attention map or an i-th vulnerability scoring map for i-th element patterns located in an i-th site image corresponding to an i-th critical pattern site in the 2D metrology image, generates i-th candidate gauge primitives by referencing the i-th attention map or the i-th vulnerability scoring map, selects at least one i-th gauge primitive from among the i-th candidate gauge primitives by referencing spatial range conditions set for the i-th element patterns, and generates the i-th_1 to i-th_m components including an i-th 3D recognition proxy component for the i-th element patterns using the at least one i-th gauge primitive.
  14. In Paragraph 13, The above i-th 3D recognition proxy component is a manufacturing process analysis device comprising at least some of Top-CD (Critical Dimension), Bottom-CD, Sidewall asymmetry information, edge asymmetry information, and profile risk indicators corresponding to the i-th specific element pattern among the i-th element patterns.
  15. In Paragraph 11, The above processor is, A manufacturing process analysis device that, in the above process (I), through component combination AI, determines k failure mechanisms or k ontologies corresponding to the i-th critical pattern site by referring to at least one of a failure mechanism template in which failure modes of a semiconductor device are defined and an ontology template in which ontology according to correlations between semiconductor manufacturing processes is defined, and generates the i-th EPE formulation to the i-th EPE formulation by combining the i-th component to the i-m component based on the determined k failure mechanisms or k ontologies.
  16. In Paragraph 11, The above processor is, A manufacturing process analysis apparatus that, in the above (II) process, matches each of the i_1 EPE formulations to the i_k EPE formulations to the at least one target performance metric through an inversion model—the inversion model is a model that estimates the yield or performance of the semiconductor substrate using the EPE—calculates the i_1 correlation between the i_1 EPE formulation and the at least one target performance metric to the i_k correlation between the i_1 EPE formulation and the at least one target performance metric, and selects each of the i_1 specific EPE formulations to the i_j specific EPE formulations among the i_1 EPE formulations to the i_k EPE formulations according to the correlation ranking determined by referring to the i_1 correlation to the i_k correlation.
  17. In Paragraph 16, A manufacturing process analysis device that, the above-mentioned inverse model generates each of the i_1 EPE maps to i_k EPE maps corresponding to each of the i_1 EPE formulations to i_k EPE formulations, and calculates the i_1 to i_k correlations, which are the correlations, by matching each of the i_1 EPE maps to i_k EPE maps with a yield map or performance map representing the yield or performance in the semiconductor substrate based on at least one target performance metric.
  18. In Paragraph 16, A manufacturing process analysis device wherein the above at least one target performance metric is a yield map or performance map for at least one level among a single layer level, a layer pair level, a die level, and a device level in the semiconductor substrate.
  19. In Paragraph 11, The above processor is, A manufacturing process analysis apparatus that, in the above process (II), if the correlations of the i_1 EPE formulation to the i_k EPE formulation correspond to a preset threshold correlation, performs a misfit diagnosis for each of the i_1 EPE formulation to the i_k EPE formulation, regenerates the i_1' EPE formulation to the i_k' EPE formulation by referring to the misfit diagnosis results, and repeats an iteration of recalculating the correlations between each of the i_1' EPE formulation to the i_k' EPE formulation and the at least one target performance metric, and if the correlations among the recalculated correlations that correspond to a threshold correlation or higher are greater than or equal to a threshold recalculation satisfaction value, selects the i_1 specific EPE formulation to the i_j specific EPE formulation from at least some of the regenerated i_1' EPE formulation to the i_k' EPE formulation.
  20. In Paragraph 19, A manufacturing process analysis device that, by referring to the misfit diagnosis result, regenerates the i_1' EPE formulation to the i_k' EPE formulation through at least one subprocess among (i) a subprocess that adjusts at least some of the selection conditions for at least one i-gauge primitive, (ii) a subprocess that adjusts at least some of the generation conditions for the i_1 component to the i_m component, and (iii) a subprocess that adjusts at least some of the combination conditions for combining the i_1 component to the i_m component.

Description

Method of determining a budget component for analyzing edge placement error in a semiconductor manufacturing process and manufacturing process analysis device using the same The present invention relates to a method for determining a budget component effective for improving yield in a semiconductor manufacturing process, and more specifically, to a method for determining a budget component for analyzing an edge placement error corresponding to the difference between edge information on a design pattern and edge information on a measurement pattern obtained by measuring the result of the semiconductor manufacturing process in a semiconductor manufacturing process, and a manufacturing process analysis device using the same. In the semiconductor manufacturing process, Edge Placement Error (EPE) is an indicator of how far a circuit pattern deviates from its designed position. Such EPEs can cause electrical defects, such as short circuits or electron leakage when patterns overlap or get too close; yield reduction, which leads to a sharp decrease in productivity due to a large number of defective chips when precision is low; and device performance degradation, which adversely affects the operating speed or reliability of semiconductors due to unstable circuit connections. Recently, as semiconductor chips have been miniaturized to the nanometer scale, the technology to stack multiple layers of circuits without error has become very important, and accordingly, EPE is one of the key performance indicators that determines the precision of the entire process, going beyond simply a single layer error. In addition, to solve the EPE problem, various process technologies such as EUV (Extreme Ultraviolet) lithography, Self-aligned Patterning, AS-ALD (Area-Selective Atomic Layer Deposition), and ALE (Atomic Layer Etching) are being introduced. Such EPE is calculated by including various components that affect pattern deformation, and is generally simplified and calculated and managed as the sum of overlay error, CD (Critical Dimension) error, and pattern curvature. In addition, conventional EPE management was primarily performed through lithography process-centered overlay control and optical proximity correction. However, in such conventional EPE management, it is difficult to identify budget components—specific components among the components used in EPE calculations that directly affect the yield of the actual semiconductor process—and consequently, there is a problem in that the root cause of yield degradation cannot be resolved. Therefore, the applicant intends to propose a method for accurately determining the budget component of EPE that reduces the yield of a semiconductor process. The drawings attached below for use in describing embodiments of the present invention are merely some of the embodiments of the present invention, and other drawings can be obtained based on these drawings without inventive work by a person skilled in the art to which the present invention pertains (hereinafter "person skilled in the art"). FIG. 1 schematically illustrates a system for determining a budget component for analyzing an edge placement error in a semiconductor manufacturing process according to an embodiment of the present invention, and FIG. 2 schematically illustrates a method for determining a budget component for analyzing an edge placement error in a semiconductor manufacturing process according to an embodiment of the present invention, and FIG. 3 illustrates, by way of example, a process of selecting at least one gauge primitive according to one embodiment of the present invention, and FIG. 4 schematically illustrates the process of generating a 3D recognition proxy component including 3D profile information for at least one gauge primitive according to an embodiment of the present invention, and FIG. 5 illustrates, in an exemplary manner, the process of redistributing the budget of specific components according to one embodiment of the present invention. The following detailed description of the invention refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that various embodiments of the invention are different but need not be mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be modified from one embodiment to another without departing from the spirit and scope of the invention. It should also be understood that the location or arrangement of individual components within each embodiment may be modified without departing from the spirit and scope of the invention. Accordingly, the following detailed description is not intended to be limited in meaning, and the scope of the invention should be understood to encompass the scope claimed by the claims and all equivalents