KR-102962912-B1 - PROGRAMMING TECHNIQUES THAT UTILIZE ANALOG BITSCAN IN A MEMORY DEVICE

Abstract

The memory device includes a memory block having a plurality of memory cells arranged in a plurality of word lines. The memory device also includes a circuit configured to program at least some of the plurality of memory cells in a selected word line among the plurality of word lines in at least one program loop of a programming operation. During at least one program loop, the circuit is configured to apply a programming pulse to the selected word line, perform a verification operation, and perform an analog bit scan operation. The circuit is also configured to determine the output of the analog bit scan operation. The output is one of at least three options. The circuit is further configured to control at least one programming parameter based on the output of the analog bit scan operation.

Inventors

• 수, 후아-링
• 친, 헨리
• 허, 얀웨이

Assignees

• 샌디스크 테크놀로지스 아이엔씨.

Dates

Publication Date

20260508

Application Date

20240110

Priority Date

20230809

Claims (20)

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2. In a method for performing programming operations on a memory device, Step of preparing a memory block comprising a plurality of memory cells arranged in a plurality of word lines—the plurality of word lines include a selected word line—; A step of programming at least some of the plurality of memory cells in at least one program loop including a programming pulse, a verification operation, and an analog bit scan operation; A step of determining the output of the analog bit scan operation above—the output is one of at least three options—; and The method includes the step of controlling at least one programming parameter based on the output of the analog bit scan operation. The above programming operation is a method in which only a single bit of data is programmed into each memory cell.
3. In paragraph 2, the method wherein the at least three options for the output of the analog bit scan operation include pass, weak failure, and strong failure.
4. In paragraph 3, the step of controlling the at least one programming parameter based on the output of the analog bit scan operation is, In response to the output of the above analog bit scan operation being a strong failure, a step of performing an additional program loop with another programming pulse, another verification operation, and another analog bit scan operation; In response to the output of the analog bit scan operation being a weak failure, a step of performing an additional program loop with another programming pulse without a verification operation and an analog bit scan operation; and A method comprising the step of terminating the programming operation for the selected word line in response to the output of the analog bit scan operation being pass.
5. In paragraph 3, the step of controlling the at least one programming parameter based on the output of the analog bit scan operation is, In response to the output of the above analog bit scan operation being a strong failure, a step of increasing the programming voltage by a first step size and performing an additional program loop; In response to the output of the analog bit scan operation being a weak failure, the step of increasing the programming voltage by a second step size and performing an additional program loop—the second step size being smaller than the first step size—; and A method comprising the step of terminating the programming operation for the selected word line in response to the output of the analog bit scan operation being pass.
6. A method according to claim 5, wherein the additional program loop does not include the verification operation or the analog bit scan operation.
7. In a method for performing programming operations on a memory device, Step of preparing a memory block comprising a plurality of memory cells arranged in a plurality of word lines—the plurality of word lines include a selected word line—; A step of programming at least some of the plurality of memory cells in at least one program loop including a programming pulse, a verification operation, and an analog bit scan operation; A step of determining the output of the analog bit scan operation above—the output is one of at least three options—; and The method includes the step of controlling at least one programming parameter based on the output of the analog bit scan operation. The above programming operation is an operation of programming at least 3 bits of data into each memory cell, and the at least 3 bits of data are associated with a plurality of data states associated with each threshold voltage range, a method.
8. In claim 7, it further includes a step of determining that programming for the second-to-last data state among the plurality of data states is completed; A method comprising the step of controlling at least one programming parameter based on the output of the analog bit scan operation, wherein the step of determining the maximum number of additional program loops to be performed before terminating the programming operation for the selected word line.
9. In paragraph 8, in response to the output of the analog bit scan operation being weak pass, the maximum number of additional program loops to be performed before terminating the programming operation for the selected word line is set to the first number of program loops; In response to the output of the analog bit scan operation being a strong pass, the maximum number of additional program loops to be performed before terminating the programming operation for the selected word line is set to a second program loop number; A method in which the number of the first program loops is greater than the number of the second program loops.
10. In paragraph 9, between program loops, the voltage of the programming pulse increases by a step size, and A method in which, between the above additional program loops, the magnitude of the step size is set as a function of the output of the analog bit scan operation.
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12. In memory devices, A memory block comprising a plurality of memory cells arranged in a plurality of word lines; In at least one program loop of a programming operation, the circuit part is configured to program at least some of the plurality of memory cells of a selected word line among the plurality of word lines, and during the at least one program loop, the circuit part, Apply a programming pulse to the selected word line, perform a verification operation, and perform an analog bit scan operation. Determine the output of the above analog bit scan operation—the output is one of at least three options—, It is configured to control at least one programming parameter based on the output of the above analog bit scan operation, and A memory device in which the above programming operation is an operation in which only a single bit of data is programmed into each memory cell of the selected word line by the circuit portion.
13. A memory device according to claim 12, wherein the at least three options for the output of the analog bit scan operation include pass, weak failure, and strong failure.
14. In paragraph 13, when controlling the at least one programming parameter based on the output of the analog bit scan operation, the circuit part, In response to the output of the above analog bit scan operation being a strong failure, an additional program loop is performed with a different programming pulse, a different verification operation, and a different analog bit scan operation; In response to the output of the above analog bit scan operation being a weak failure, an additional program loop is performed with another programming pulse without a verification operation and an analog bit scan operation; A memory device configured to terminate the programming operation for the selected word line in response to the output of the analog bit scan operation being pass.
15. In paragraph 13, when controlling the at least one programming parameter based on the output of the analog bit scan operation, the circuit part, In response to the output of the above analog bit scan operation being a strong failure, the programming voltage is increased by a first step size and an additional program loop is performed; In response to the output of the above analog bit scan operation being a weak failure, the programming voltage is increased by a second step size, and an additional program loop is performed—the second step size is smaller than the first step size—; and A memory device configured to terminate the programming operation for the selected word line in response to the output of the analog bit scan operation being pass.
16. In memory devices, A memory block comprising a plurality of memory cells arranged in a plurality of word lines; In at least one program loop of a programming operation, the circuit part is configured to program at least some of the plurality of memory cells of a selected word line among the plurality of word lines, and during the at least one program loop, the circuit part, Apply a programming pulse to the selected word line, perform a verification operation, and perform an analog bit scan operation. Determine the output of the above analog bit scan operation—the output is one of at least three options—, It is configured to control at least one programming parameter based on the output of the above analog bit scan operation, and A memory device, wherein the above programming operation is an operation in which at least 3 bits of data are programmed into each memory cell by the circuit portion, and the at least 3 bits of data are associated with a plurality of data states associated with each threshold voltage range.
17. In paragraph 16, the circuit determines that programming for the second-to-last data state among the plurality of data states is completed, and A memory device further configured to determine the maximum number of additional program loops to be performed before terminating the programming operation for the selected word line.
18. In paragraph 17, in response to the output of the analog bit scan operation being weak pass, the maximum number of additional program loops to be performed before terminating the programming operation for the selected word line is set to the first number of program loops; In response to the output of the analog bit scan operation being a strong pass, the maximum number of additional program loops to be performed before terminating the programming operation for the selected word line is set to a second program loop number; A memory device in which the number of the first program loops is greater than the number of the second program loops.
19. In paragraph 18, between program loops, the circuit increases the voltage of the programming pulse by the step size, and A memory device, wherein, between the above additional program loops, the circuit portion sets the size of the step size as a function of the output of the analog bit scan operation.
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Description

Programming Techniques That Utilize Analog Bitscan in a Memory Device Cross-reference regarding related applications This application claims the benefit of U.S. Provisional Application No. 63/523,955 filed June 29, 2023. The full disclosure of the application referenced above is incorporated by reference into this application. 1. Technology Field The present disclosure generally relates to the operation of non-volatile memory, and in particular to programming techniques for improving performance, reliability, and/or durability. 2. Prior Art Semiconductor memory is widely used in various electronic devices such as mobile phones, digital cameras, personal handheld devices, medical electronic devices, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memory may include non-volatile memory or volatile memory. Non-volatile memory enables information to be stored and retained even when the non-volatile memory is not connected to a power source, for example, a battery. A NAND memory device comprises a chip having multiple memory blocks, each of which comprises an array of memory cells arranged in multiple word lines. Programming of the memory cells in the word lines to retain data typically occurs in multiple program loops, each program loop comprising a verification operation for applying a programming pulse to a control gate of the word line and optionally detecting a threshold voltage of the memory cell to be programmed. Each program loop may also include a pre-charge operation prior to the programming pulse to pre-charge multiple channels containing the memory cells to be programmed. One aspect of the present disclosure relates to a method for performing a programming operation in a memory device. The method comprises the step of preparing a memory block comprising a plurality of memory cells arranged in a plurality of word lines. The plurality of word lines includes a selected word line. The method continues to the step of programming at least some of the plurality of memory cells in at least one program loop comprising a programming pulse, a verification operation, and an analog bit scan operation. The method proceeds to the step of determining the output of the analog bit scan operation. The output is one of at least three options. The method continues to the step of controlling at least one programming parameter based on the output of the analog bit scan operation. According to another aspect of the present disclosure, the programming operation is an operation in which only a single bit of data is programmed into each memory cell. According to another aspect of the present disclosure, at least three options for the output of an analog bit scan operation include pass, weak fail, and strong fail. According to another aspect of the present disclosure, the step of controlling at least one programming parameter based on the output of an analog bitscan operation comprises the following potential actions. In response to the output of the analog bitscan operation being a strong failure, the method continues to the step of performing an additional program loop using a different programming pulse, a different verification operation, and a different analog bitscan operation. In response to the output of the analog bitscan operation being a weak failure, the method continues to the step of performing an additional program loop using a different programming pulse without a verification operation and an analog bitscan operation. In response to the output of the analog bitscan operation being a pass, the method continues to the step of terminating the programming operation for a selected word line. According to another aspect of the present disclosure, the step of controlling at least one programming parameter based on the output of an analog bitscan operation comprises the following potential actions. In response to the output of the analog bitscan operation being a strong failure, the method continues to the step of increasing the programming voltage by a first step size. In response to the output of the analog bitscan operation being a weak failure, the method continues to the step of increasing the programming voltage by a second step size and performing an additional program loop without program verification or an analog bitscan operation, wherein the second step size is smaller than the first step size. In response to the output of the analog bitscan operation being a pass, the method continues to the step of terminating the programming operation for a selected word line. According to another aspect of the present disclosure, the programming operation is an operation of programming at least 3 bits of data into each memory cell. The at least 3 bits of data are associated with a plurality of data states associated with each threshold voltage range. According to another aspect of the present disclosure, the method continues to the step of determining