KR-102962925-B1 - SEMICONDUCTOR DEVICE AND DATA READING METHOD USING THEREFORE

Abstract

A semiconductor device according to an embodiment includes a memory that stores data in a non-volatile manner and a volatile manner, and a memory controller that controls the memory. The memory may include a wordline pair comprising a first wordline and a second wordline, a first bitline pair orthogonal to the first wordline and the second wordline and comprising a first bitline and a first complementary bitline, and a memory cell pair comprising a first memory cell and a second memory cell adjacent to the first memory cell in the wordline direction. The first memory cell and the second memory cell may each store data in a volatile manner. The left node of the first memory cell connected to the first bit line, the right node of the first memory cell connected to the first complementary bit line, and the left node of the second memory cell are all connected to the first word line selected among the first word line and the second word line, and a data value stored in the memory cell pair in a non-volatile manner can be determined according to the selected first word line to which the left node of the first memory cell, the right node of the first memory cell, and the left node of the second memory cell are connected.

Inventors

• 이동수
• 김대현
• 위구연

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20190821

Claims (20)

1. delete
2. Memory that stores data in non-volatile and volatile modes; and It includes a memory controller that controls the above memory, and the memory is: A wordline pair including a first wordline and a second wordline; A first bitline pair orthogonal to the first wordline and the second wordline, comprising a first bitline and a first complementary bitline; and A memory cell pair comprising a first memory cell and a second memory cell adjacent to the first memory cell in a wordline direction, wherein the first memory cell and the second memory cell each store data in a volatile manner, and The left node of the first memory cell connected to the first bit line, the right node of the first memory cell connected to the first complementary bit line, and the left node of the second memory cell are all connected to one word line selected among the first word line and the second word line, and Depending on which word line the left node of the first memory cell, the right node of the first memory cell, and the left node of the second memory cell are connected to, a data value stored in the memory cell pair in a non-volatile manner is determined, and The memory controller provides a read voltage to the first word line and a read prohibition voltage to the second word line, determines the voltage level of the first bit line connected to the first memory cell and the voltage level of the first complementary bit line connected to the first memory cell, and determines the value of data stored in the memory cell pair in a non-volatile manner based on whether the voltage level of the first bit line and the voltage level of the first complementary bit line are both above a predetermined threshold value. A left-connecting transistor connecting the left node of the first memory cell and the first bit line, and a right-connecting transistor connecting the right node of the first memory cell and the first complementary bit line, are connected together to the selected first word line. A semiconductor device in which the left-connected transistor and the right-connected transistor are opened and closed together in response to a voltage applied to the selected first word line.
3. In paragraph 2, A semiconductor device in which the above-mentioned read voltage is a power supply voltage and the above-mentioned read prohibition voltage is a ground power supply voltage.
4. In paragraph 2, A semiconductor device in which the memory controller determines a data value stored in the memory cell pair in a non-volatile manner as 1 if both the voltage level of the first bit line and the voltage level of the first complementary bit line are greater than or equal to a predetermined threshold value.
5. delete
6. delete
7. delete
8. delete
9. delete
10. delete
11. In a method for a semiconductor device to read data stored in memory in a non-volatile manner, For a wordline pair comprising a first wordline and a second wordline, the step of providing a read voltage to the first wordline and providing a read prohibition voltage to the second wordline; A step of determining the voltage level of a first bit line connected to a first memory cell included in the memory and the voltage level of a first complementary bit line connected to the first memory cell; and The method includes the step of reading out the value of data stored in the first memory cell in a non-volatile manner based on whether the voltage level of the first bit line and the voltage level of the first complementary bit line are both above a predetermined threshold value. A left-connecting transistor connecting the left node of the first memory cell and the first bit line, and a right-connecting transistor connecting the right node of the first memory cell and the first complementary bit line, are connected together to one word line selected among the first word line and the second word line. A method in which the left-connected transistor and the right-connected transistor are opened and closed together in response to a voltage applied to a single word line in which the left-connected transistor and the right-connected transistor are connected together.
12. In claim 11, the method wherein the first bit line and the first complementary bit line are orthogonal to the first word line and the second word line.
13. In Paragraph 11, A method in which the above-mentioned reading voltage is a power supply voltage and the above-mentioned reading prohibition voltage is a ground power supply voltage.
14. In Paragraph 11, A method comprising the step of reading the value of data stored in a non-volatile manner in the first memory cell, wherein if the voltage level of the first bit line and the voltage level of the first complementary bit line are both greater than or equal to a predetermined threshold value, the step of determining the data value stored in a non-volatile manner in the first memory cell as 1.
15. In Paragraph 11, The above first memory cell is a Static Random Access Memory (SRAM) cell, method.
16. In claim 11, the method wherein the first memory cell is composed of a latch circuit comprising four transistors.
17. In Paragraph 11, A method wherein the right node of the first memory cell is electrically connected to the first word line through the gate region of the right-connected transistor of the first memory cell, and the left node of the first memory cell is electrically connected to the first word line through the gate region of the left-connected transistor of the first memory cell.
18. In Paragraph 17, The above memory includes a second memory cell adjacent to the first memory cell in the wordline direction, and A method in which the right node of the first memory cell and the left node of the second memory cell are electrically connected through the right-connecting transistor of the first memory cell and the left-connecting transistor of the second memory cell.
19. A method according to claim 18, wherein the right node of the first memory cell and the left node of the second memory cell are electrically connected through a contact via formed between the gate region of the right-connected transistor of the first memory cell and the gate region of the left-connected transistor of the second memory cell.
20. In Paragraph 11, A method further comprising an addition circuit connected to the first bit line and the first complementary bit line, and performing an addition operation on a logic value corresponding to a voltage level appearing in the first bit line and the first complementary bit line.

Description

Semiconductor Device and Data Reading Method Using Thereof The present disclosure relates to a semiconductor device and a data storage method using the same, and more specifically, to a storage method of a semiconductor device for storing non-volatile data and volatile data. Computer systems can include various types of memory systems. In a computer system, semiconductor devices can be used as main memory. Main memory may include random access memory, which is written to or read randomly at high access speeds. Data storage devices using semiconductors can be implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Semiconductor devices can be broadly classified into volatile memory devices and non-volatile memory devices. Volatile memory devices are memory devices in which stored data is lost when the power supply is cut off. Non-volatile memory devices are memory devices that retain stored data even when the power supply is cut off. Volatile memory devices may include Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). SRAM offers lower power consumption and faster operation characteristics compared to DRAM, and is widely used as cache memory devices in computers or in portable electronic products. Meanwhile, as the methods of utilizing data stored in memory devices diversify, there is increasing demand for hybrid memory devices capable of storing both non-volatile and volatile data. The present disclosure can be easily understood from the combination of the following detailed description and the accompanying drawings, where reference numerals denote structural elements. FIG. 1 is a block diagram of a semiconductor device according to one embodiment. FIG. 2 is a diagram illustrating an equivalent circuit diagram of an SRAM cell according to one embodiment. FIG. 3 is a drawing illustrating a memory cell pair according to one embodiment. FIG. 4a is a diagram illustrating an example of memory cell pairs that store 4 bits of data in a non-volatile manner. Figure 4b is a diagram illustrating the structure of the memory cell pairs of Figure 4a. FIG. 5 is a flowchart illustrating a method for reading data stored in a memory cell in a volatile manner according to one embodiment. FIG. 6 is a flowchart illustrating a method of storing data in a memory cell in a volatile manner according to one embodiment. FIG. 7 is a flowchart illustrating a method for reading data stored in a memory cell in a non-volatile manner according to one embodiment. FIG. 8 is a drawing illustrating a memory cell pair according to one embodiment. FIG. 9 is a drawing illustrating a plurality of memory cell pairs according to one embodiment. FIG. 10 is a drawing illustrating a plurality of memory cells according to one embodiment. FIG. 11 is a flowchart illustrating a method for reading data stored in a non-volatile manner in a memory cell pair according to one embodiment. FIG. 12 is a diagram illustrating a logical expression for determining data stored in a non-volatile manner in a memory cell pair according to one embodiment. FIG. 13 is a block diagram illustrating an electronic device including a semiconductor device according to one embodiment. FIG. 14 is a block diagram illustrating an electronic device according to one embodiment. FIG. 15 is a drawing illustrating a circuit block of an electronic device according to one embodiment. Embodiments of the present disclosure are described below in detail with reference to the attached drawings so that those skilled in the art can easily implement them. However, the present disclosure may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present disclosure in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification are denoted by similar reference numerals. Some embodiments of the present disclosure may be represented by functional block configurations and various processing steps. Some or all of these functional blocks may be implemented by various numbers of hardware and/or software configurations that execute specific functions. For example, the functional blocks of the present disclosure may be implemented by one or more microprocessors or by circuit configurations for a specific function. Additionally, for example, the functional blocks of the present disclosure may be implemented in various programming or scripting languages. The functional blocks may be implemented as algorithms executed on one or more processors. Furthermore, the present disclosure may employ prior art for electronic configuration, signal processing, and/or data processing, etc. Furthermore, the connecting lines or connecting members between the components depicted in the drawings are merely illustrative of functional connections and/or physical or circuit connections. In the actual de