KR-102962949-B1 - MEMORY DEVICE

Abstract

A memory device according to one embodiment of the present invention includes a cell region in which a plurality of memory blocks, each comprising a plurality of memory cells, are arranged, and peripheral circuits that control the cell region, and includes a peripheral circuit region that performs an erase operation on each of the memory blocks as a unit, wherein each of the memory blocks includes a plurality of word lines stacked on a substrate, a plurality of channel structures extending in a first direction perpendicular to the upper surface of the substrate and penetrating the plurality of word lines, and a source region formed on the substrate and connected to the plurality of channel structures, and wherein, while the erase operation is performed by inputting an erase voltage to the source region of a target memory block among the memory blocks, the peripheral circuit region reduces the voltage of a first word line from a first bias voltage to a second bias voltage at a first time point, and reduces the voltage of a second word line different from the first word line from a third bias voltage to a fourth bias voltage at a second time point different from the first time point.

Inventors

• 이요한
• 남상완
• 박상원

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260512

Application Date

20200922

Claims (20)

1. A cell region in which a plurality of memory blocks, each comprising a plurality of memory cells, are arranged; and A peripheral circuit region comprising peripheral circuits that control the cell region and perform an erase operation on each of the memory blocks as a unit; Each of the above memory blocks comprises a plurality of word lines stacked on a substrate, a plurality of channel structures extending in a first direction perpendicular to the upper surface of the substrate and penetrating the plurality of word lines, and a source region formed on the substrate and connected to the plurality of channel structures. The above peripheral circuit region, while executing the erase operation by inputting an erase voltage to the source region of the target memory block among the memory blocks, reduces the voltage of the first word line from the first bias voltage to the second bias voltage at a first time point, and reduces the voltage of the second word line, which is different from the first word line, from the third bias voltage to the fourth bias voltage at a second time point different from the first time point. A memory device wherein the peripheral circuit region includes a plurality of pass elements connected to the word lines, and sequentially inputs a first turn-on voltage and a second turn-on voltage smaller than the first turn-on voltage to the gate terminal of each of the plurality of pass elements during the erasure operation.
2. In paragraph 1, A memory device in which the second word line is positioned between the first word line and the substrate in the first direction, and the second time point is later than the first time point.
3. In paragraph 1, A memory device in which the first word line comprises a plurality of first word lines, and the second word line comprises a plurality of second word lines.
4. delete
5. In paragraph 1, A memory device in which the first turn-on voltage is input to the gate terminal of each of the plurality of pass elements during a transition period in which the voltage of the source region increases to the erase voltage, and the second turn-on voltage is input to the gate terminal of each of the plurality of pass elements during a hold period in which the voltage of the source region is maintained at the erase voltage.
6. In paragraph 1, A memory device in which the first bias voltage and the third bias voltage have different levels.
7. In paragraph 1, A memory device in which the second bias voltage and the fourth bias voltage have different levels.
8. In paragraph 1, The erase time during which the above erase operation is executed includes a transition period during which the voltage of the source region increases to the erase voltage, and a hold period during which the voltage of the source region is maintained at the erase voltage. The above first time point and the above second time point are memory devices belonging to the above hold interval.
9. In paragraph 8, Each of the above memory blocks includes string selection lines disposed above the word lines, and ground selection lines disposed below the word lines, and The above peripheral circuit region is a memory device that turns off the string selection lines until a first turn-on point belonging to the transition interval and inputs a first suppression voltage after the first turn-on point, and turns off the ground selection line until a second turn-on point belonging to the transition interval and inputs a second suppression voltage after the second turn-on point.
10. In Paragraph 9, A memory device in which the levels of the first suppression voltage and the second suppression voltage, respectively, are greater than the levels of the first bias voltage and the third bias voltage.
11. In paragraph 1, The above peripheral circuit area sequentially executes a first erasure operation, a verification operation, and a second erasure operation, and A memory device in which the first erasure operation is the erasure operation, and the verification operation includes the operation of reading data of the plurality of memory cells included in the target memory block after the first erasure operation.
12. In Paragraph 11, The above peripheral circuit region is a memory device that, in the second erasure operation, reduces the voltage of the first word line from the first bias voltage to the second bias voltage at a third time point and inputs a suppression voltage greater than the first bias voltage to the second word line.
13. In Paragraph 11, The above peripheral circuit region is a memory device that, in the second erasure operation, reduces the voltage of the first word line from the fifth bias voltage to the sixth bias voltage at the third time point, and reduces the voltage of the second word line from the seventh bias voltage to the eighth bias voltage at the fourth time point, which is different from the third time point.
14. Multiple word lines stacked on a substrate; A plurality of channel structures extending in a first direction perpendicular to the upper surface of the substrate and penetrating the plurality of word lines; A source region formed on the substrate and connected to the plurality of channel structures; Separation layers that divide the above plurality of word lines into a plurality of memory blocks; and A peripheral circuit region that inputs an erase voltage to the source region in an erase operation executed as a unit for each of the plurality of memory blocks; is included, The plurality of wordlines each include a first wordline group and a second wordline group, each comprising two or more wordlines, and the second wordline group is disposed between the first wordline group and the substrate, and A memory device in which the above peripheral circuit region inputs the same voltage to the first wordline group and the second wordline group while the voltage of the source region increases to the erase voltage, and while the voltage of the source region is maintained at the erase voltage, the voltage input to the first wordline group decreases at an earlier time than the voltage input to the second wordline group.
15. In Paragraph 14, It includes a first erasure control line disposed below the plurality of word lines, and a second erasure control line disposed above the plurality of word lines, A memory device wherein each of the plurality of channel structures comprises a channel layer, the channel layer comprising a first channel layer adjacent to the plurality of word lines, and a second channel layer adjacent to the first erase control line and the second erase control line and having a conductivity different from that of the first channel layer.
16. In paragraph 15, The above second channel layer is a memory device doped with N-type impurities.
17. In Paragraph 14, Each of the plurality of channel structures includes a channel layer, wherein the channel layer includes a first region penetrating the first wordline group and a second region penetrating the second wordline group, and A memory device in which the width of the first region is larger than the width of the second region.
18. A cell region in which a plurality of memory blocks are disposed, each comprising a plurality of word lines stacked on a substrate, a plurality of channel layers extending in a first direction perpendicular to the upper surface of the substrate and penetrating the plurality of word lines, and a source region formed on the substrate and connected to the plurality of channel layers; and A peripheral circuit region comprising peripheral circuits that control the cell region and perform an erase operation on each of the memory blocks as a unit; The erase time during which an erase voltage is input to the source region includes a transition period during which the voltage of the source region increases to the erase voltage and a hold period during which the voltage of the source region is maintained at the erase voltage. A memory device wherein the above peripheral circuit region sets the voltage difference between the word lines and the plurality of channel layers to a first level during a first time period of the hold interval, sets the voltage difference between some of the word lines and the plurality of channel layers to a second level greater than the first level during a second time period after the first time period, and sets the voltage difference between the word lines and the plurality of channel layers to the second level during a third time period after the second time period.
19. In Paragraph 18, The substrate included in the cell region is a first substrate, and the peripheral circuit region includes a second substrate different from the first substrate on which the peripheral circuits are arranged, and A memory device in which the cell region and the peripheral circuit region are stacked in a direction perpendicular to the upper surface of the first substrate.
20. In Paragraph 19, The cell region includes first metal pads, and the peripheral circuit region includes second metal pads, and A memory device in which the cell region and the peripheral circuit region are connected to each other in a direction perpendicular to the upper surface of the first substrate by the first metal pads and the second metal pads.

Description

Memory Device The present invention relates to a memory device. A memory device can provide functions for writing and erasing data, or reading recorded data. To accurately read data recorded in a memory device, it is necessary to appropriately control the variation of the threshold voltage according to the data recorded in each memory cell. If the variation of the threshold voltage of the memory cells is not properly controlled after an erase operation to delete recorded data, the variation of the memory cells may also deteriorate after a program operation, potentially leading to a decrease in the performance of the memory device. FIG. 1 is a simplified diagram showing a memory device according to one embodiment of the present invention. FIGS. 2 and FIGS. 3 are drawings that simply illustrate a memory device according to an embodiment of the present invention. FIG. 4 is a drawing provided to explain the operation of a memory device according to one embodiment of the present invention. FIG. 5 is a simplified diagram of a memory device according to one embodiment of the present invention. FIGS. 6 to 9 are drawings provided to explain the operation of a memory device according to embodiments of the present invention. FIGS. 10 to 12 are drawings showing comparative examples for explaining the operation of a memory device according to embodiments of the present invention. FIGS. 13 to 16 are drawings provided to explain the operation of a memory device according to embodiments of the present invention. FIGS. 17 and FIGS. 18 are drawings that simply illustrate a memory device according to one embodiment of the present invention. FIG. 19 is a simplified drawing of a memory device according to one embodiment of the present invention. FIG. 20 is a drawing provided to explain the operation of a memory device according to embodiments of the present invention. FIG. 21 is a simplified drawing of a memory device according to one embodiment of the present invention. FIG. 22 is a drawing provided to explain the operation of a memory device according to embodiments of the present invention. FIGS. 23 and FIGS. 24 are drawings that simply illustrate a memory device according to one embodiment of the present invention. FIG. 25 is a block diagram showing a memory system according to one embodiment of the present invention. Hereinafter, preferred embodiments of the present invention are described as follows with reference to the attached drawings. FIG. 1 is a simplified diagram showing a memory device according to one embodiment of the present invention. Referring to FIG. 1, the memory device (10) may include a cell area (20) and a peripheral circuit area (30). The peripheral circuit area (30) may include a row decoder (31), a voltage generator (32), a page buffer (33), an input/output circuit (34), and control logic (35), etc. The cell region (20) includes a plurality of memory cells and can be divided into a plurality of blocks (BLK1-BLKn). The plurality of blocks (BLK1-BLKn) can be connected to a row decoder (31) via common source lines (CSL), string select lines (SSL), word lines (WL), and ground select lines (GSL), and can be connected to a page buffer (33) via bit lines (BL). For example, in each of the blocks (BLK1-BLKn), a plurality of memory cells arranged at the same height from the substrate can be connected to the same word line (WL), and a plurality of memory cells placed at the same position in a plane parallel to the upper surface of the substrate can provide a memory cell string that shares a single channel layer. Additionally, some of the memory cell strings included in each of the blocks (BLK1-BLKn) can be connected to the same bit line (BL). The row decoder (31) can decode address data (ADDR) received from the control logic (35), etc., to generate and transmit voltages for driving the word lines (WL). The row decoder (31) can input the word line voltage generated by the voltage generator (32) to the word lines (WL) in response to the control of the control logic (35). For example, the row decoder (31) is connected to the word lines (WL) through pass transistors, and can input the word line voltage to the word lines (WL) when the pass transistors are turned on. The page buffer (33) is connected to the cell area (20) via bit lines (BL) and can read data stored in memory cells or write data to memory cells. The page buffer (33) may include a column decoder, a latch circuit, etc. The column decoder can select at least some of the bit lines (BL) of the cell area (20), and the latch circuit can read data from the memory cell connected to the bit line (BL) selected by the column decoder during a read operation. The input/output circuit (34) can receive data (DATA) during program operation and transmit it to the page buffer (33), and during a read operation, the page buffer (33) can output the data (DATA) read from the cell area (30) to the outside. The input/output circuit (34) can transmit an address or command recei