KR-102962950-B1 - SEMICONDUCTOR PACKAGE

KR102962950B1KR 102962950 B1KR102962950 B1KR 102962950B1KR-102962950-B1

Abstract

One embodiment of the present invention comprises: a substrate including a redistribution layer; a chip structure including a first semiconductor chip disposed on the substrate and including a first through-electrode, a second semiconductor chip disposed on the first semiconductor chip and electrically connected to the first semiconductor chip through the first through-electrode, and a first sealing material surrounding the second semiconductor chip; a first connecting bump disposed between the substrate and the chip structure and electrically connecting the first through-electrode and the redistribution layer; and a second connecting bump disposed below the substrate and electrically connected to the redistribution layer. A semiconductor package is provided that includes a second sealing material for sealing the chip structure on the substrate, wherein the first semiconductor chip has a first upper surface on which a first upper pad is disposed and a first lower surface on which a first lower pad electrically connected to the first upper pad through the first through electrode is disposed, and the second semiconductor chip has a second lower surface on which a second lower pad electrically connected to the first upper pad is disposed, and the second lower surface of the second semiconductor chip is in direct contact with the first upper surface of the first semiconductor chip.

Inventors

장재권
석경림
송인형

Assignees

삼성전자주식회사

Dates

Publication Date: 20260512
Application Date: 20210903

Claims (10)

A substrate including a first redistribution layer; A chip structure comprising a first semiconductor chip disposed on the substrate and including a first through-electrode, a second semiconductor chip disposed on the first semiconductor chip and electrically connected to the first semiconductor chip through the first through-electrode, and a first sealing material surrounding the second semiconductor chip; A first connecting bump disposed between the substrate and the chip structure and electrically connecting the first through electrode and the first redistribution layer; A second connection bump disposed below the substrate and electrically connected to the first redistribution layer; A second sealant for sealing the chip structure on the substrate; A redistribution structure disposed on the second suture material and comprising a second redistribution layer; and It includes a connecting structure that penetrates the second sealing material and electrically connects the first redistribution layer and the second redistribution layer, The first semiconductor chip has a first upper surface on which a first upper pad is disposed and a first lower surface on which a first lower pad is disposed that is electrically connected to the first upper pad through the first through electrode. The second semiconductor chip has a second lower surface on which a second lower pad electrically connected to the first upper pad is disposed. A semiconductor package in which the second lower surface of the second semiconductor chip is in direct contact with the first upper surface of the first semiconductor chip.
In Article 1, The first semiconductor chip is a semiconductor package having a width greater than the width of the second semiconductor chip in a direction parallel to the upper surface of the substrate.
In Article 1, The first sealing material is a semiconductor package in contact with at least a portion of the first upper surface of the first semiconductor chip and the side of the second semiconductor chip.
In Article 1, The semiconductor package, wherein the second semiconductor chip has a second upper surface on which a second upper pad is disposed, and further includes a second through-electrode that electrically connects the second upper pad and the second lower pad.
In Paragraph 4, The above chip structure further includes a third semiconductor chip disposed on the second semiconductor chip and having a third lower surface disposed thereon having a third lower pad electrically connected to the second upper pad. The third lower surface of the third semiconductor chip is a semiconductor package that directly contacts the second upper surface of the second semiconductor chip.
A substrate including a first redistribution layer; A chip structure comprising semiconductor chips disposed on the upper surface of the substrate and stacked in a direction perpendicular to the upper surface of the substrate, and a first sealing material surrounding the sides of at least some of the semiconductor chips; A connecting bump disposed between the substrate and the chip structure and electrically connecting the semiconductor chips to the first redistribution layer; A second sealant for sealing the chip structure on the substrate; A redistribution structure disposed on the second suture material and comprising a second redistribution layer; and It includes a connecting structure that penetrates the second sealing material and electrically connects the first redistribution layer and the second redistribution layer, The above chip structure has a lower surface spaced apart from the upper surface of the substrate, and The second sealing material fills the space between the lower surface of the chip structure and the upper surface of the substrate, and surrounds the side of the connection bump in the semiconductor package.
In Article 6, The first and second sealing materials above are semiconductor packages comprising the same type of insulating material.
A substrate including a first redistribution layer; A chip structure comprising semiconductor chips disposed on the upper surface of the substrate and stacked in a direction perpendicular to the upper surface of the substrate, and a first sealing material surrounding the sides of at least some of the semiconductor chips; A connecting bump disposed between the substrate and the chip structure and electrically connecting the semiconductor chips to the redistribution layer; A second sealant covering the upper and lower surfaces of the above chip structure; A redistribution structure comprising an insulating layer disposed on the second sealing material and a second redistribution layer on the insulating layer; and A semiconductor package comprising a connecting structure that electrically connects the first redistribution layer and the second redistribution layer by penetrating the second sealing material.
In Article 8, A semiconductor package in which the above-described redistribution structure further includes a redistribution via that penetrates the insulating layer and electrically connects the second redistribution layer and the connection structure.
In Article 8, A semiconductor package further comprising a cover layer covering the second redistribution layer on the redistribution structure and having an opening that exposes at least a portion of the second redistribution layer.

Description

Semiconductor Package {SEMICONDUCTOR PACKAGE} The present invention relates to a semiconductor package. With the miniaturization and increased performance of electronic devices, there is a growing demand for the development of miniaturized and high-performance semiconductor packages in the field of semiconductor packaging. To achieve miniaturization, lightweighting, high performance, and high reliability in semiconductor packages, research and development on semiconductor packages with a multi-layered stacked structure are continuously being conducted. FIG. 1a is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention, and FIG. 1b is a plan view illustrating a cross-sectional plane along line II' of FIG. 1a. FIG. 2 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. FIG. 5a is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention, and FIG. 5b is a plan view illustrating a cross-sectional plane along the line II-II' of FIG. 5a. FIG. 6a is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention, and FIG. 6b is a plan view illustrating a cross-sectional plane along the line III-III' of FIG. 6a. FIG. 7 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. FIGS. 8a to 8c are cross-sectional views illustrating the manufacturing process of a chip structure applied to a semiconductor package of one embodiment in the order of process. FIGS. 9a to 9d are cross-sectional views illustrating the manufacturing process of a semiconductor package of one embodiment in the order of process. Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings. FIG. 1a is a cross-sectional view illustrating a semiconductor package (1000A) according to one embodiment of the present invention, and FIG. 1b is a plan view illustrating a cross-sectional plane along the line I-I' of FIG. 1a. Referring to FIGS. 1a and 1b, a semiconductor package (1000A) of one embodiment may include a chip structure (CS) and a substrate (500) on which the chip structure (CS) is mounted. Here, the chip structure (CS) is formed by stacking two or more semiconductor chips (e.g., 100, 200) in a direction perpendicular to the mounting surface of the substrate (500) (Z-axis direction), and the semiconductor chips (e.g., 100, 200) may be electrically connected to each other by through silicon vias (TSVs). In order to mount such a chip structure (CS) on a main board of an electronic component, it is necessary to package it in a fan-out form. For example, when a rewiring circuit is integratedly formed on the lower surface of a chip structure (CS) where the lower pad (104) of the lowest semiconductor chip (100) is exposed after the upper and side surfaces of the chip structure (CS) are first sealed, undulation occurs due to the thickness of the chip structure (CS), making it difficult to form a fine-pitch rewiring circuit. On the other hand, according to the present invention, by mounting a chip structure (CS) having a substantial thickness on a separately manufactured substrate (500) in a flip-chip manner, the chip structure (CS) can be rewired through a fine-pitch rewiring circuit, and the yield of the semiconductor package (1000A) containing the chip structure (CS) can be improved. Accordingly, a semiconductor package (1000A) of one embodiment may further include a first connection bump (B1) that electrically connects a chip structure (CS) to a redistribution layer (512) of a substrate (500), and a second connection bump (B2) that serves as an external connection terminal on the lower surface of the substrate (500). For example, the semiconductor package (1000A) may further include a second sealing material (520) that seals the chip structure (CS) on the substrate (500). In this case, the chip structure (CS) has a lower surface spaced apart from the upper surface (500US) of the substrate (500), and the second sealing material (520) may be formed to fill the space between the lower surface of the chip structure (CS) and the upper surface (500US) of the substrate (500) and to surround the side of the first connection bump (B1). It can be understood that the lower surface of the chip structure (CS) refers to the same surface as the lower surface (100LS) of the lowest semiconductor chip, for example, the first semiconductor chip (100). Hereinafter, each element constituting the semiconductor package (1000A) of one embodiment will be described in detail. A chip str