KR-102962951-B1 - FILM PACKAGE

KR102962951B1KR 102962951 B1KR102962951 B1KR 102962951B1KR-102962951-B1

Abstract

One embodiment of the present invention comprises: a film substrate having opposing first and second surfaces, wherein the first surface includes a first region and a second region spaced apart in a first direction parallel to the first surface; a plurality of wiring patterns each including an input pattern extending from the first region to a first side of the film substrate, an output pattern extending from the second region to a second side of the film substrate opposite to the first side, and an interconnection pattern extending from the first region to the second region; a first semiconductor chip mounted on the first region and electrically connected to the input pattern and the interconnection pattern; a second semiconductor chip mounted on the second region and connected to the interconnection pattern and the output pattern; and a protective layer disposed on the first surface to cover at least a portion of the plurality of wiring patterns, and including a first opening that exposes at least a portion of the first region, a second opening that exposes at least a portion of the second region, and a third opening that exposes at least a portion of the input pattern adjacent to the first side. A film package is provided comprising: a first conductive film disposed on the protective layer between the first opening and the third opening and extending in a second direction intersecting the first direction on a plane; and a second conductive film disposed on the second surface to overlap with the first conductive film in a third direction perpendicular to the first surface.

Inventors

조성은
정재민
김재춘
류승걸
오경석

Assignees

삼성전자주식회사

Dates

Publication Date: 20260511
Application Date: 20211202

Claims (10)

A film substrate having opposing first and second surfaces, wherein the first surface includes a first region and a second region spaced apart in a first direction parallel to the first surface; A plurality of wiring patterns, each comprising an input pattern extending from the first region to the first side of the film substrate, an output pattern extending from the second region to the second side of the film substrate opposite to the first side, and an interconnection pattern extending from the first region to the second region; A first semiconductor chip mounted on the first region and electrically connected to the input pattern and the interconnection pattern; A second semiconductor chip mounted on the second region and connected to the interconnection pattern and the output pattern; A protective layer disposed on the first surface to cover at least a portion of the plurality of wiring patterns, comprising a first opening that exposes at least a portion of the first region, a second opening that exposes at least a portion of the second region, and a third opening that exposes at least a portion of the input pattern adjacent to the first side; A first conductive film disposed on the protective layer between the first opening and the third opening and extending in a second direction intersecting the first direction in a plane; and A film package comprising a second conductive film disposed on the second surface so as to overlap with the first conductive film in a third direction perpendicular to the first surface.
In Article 1, The first conductive film is a film package having a bar shape extended in the longitudinal direction of the first semiconductor chip.
In Article 1, The first conductive film is a film package having a width equal to or smaller than the width between the first opening and the third opening.
In Article 1, The first conductive film has a first corner adjacent to the first side, and The second conductive film has a second corner adjacent to the first side, and The first and second corners are film packages located substantially on the same line in the third direction.
In Article 1, The protective layer between the first opening and the second opening is a film package exposed from the first conductive film.
In Article 1, The second conductive film is a film package positioned closer to the first side than to the second side.
In Article 6, The protective layer further comprises a fourth opening that exposes at least a portion of the output pattern adjacent to the second side.
A film substrate having a first side and a second side facing in a first direction; A first semiconductor chip mounted on the above film substrate; At least one second semiconductor chip mounted on the film substrate and spaced apart from the first semiconductor chip in the first direction; A first conductive film disposed on the film substrate between the first semiconductor chip and the first side; and It includes a second conductive film disposed below the film substrate in the first direction so as to be adjacent to the first side than the second side, and which overlaps with at least a portion of the first conductive film in a vertical direction. The first semiconductor chip has a first long side, a second long side, a first short side, and a second short side, and The first long side and the second long side are opposite to each other in the first direction, and The first short side and the second short side are opposite to each other in a second direction perpendicular to the first direction, and The first long side faces the first side of the film substrate, and The first conductive film is adjacent to one or more of the first long side, the first short side, or the second short side, excluding the second long side, and A film package in which the upper surface of the first conductive film is located at a lower level than the upper surface of the first semiconductor chip.
In Article 8, The first conductive film is a film package having a width in the range of 1 mm to 10 mm in the first direction.
A film substrate having a first side and a second side facing in a first direction; A first semiconductor chip mounted on the film substrate so as to be adjacent to the first side; A second semiconductor chip mounted on the film substrate so as to be adjacent to the second side; A first conductive film disposed on the film substrate between the first semiconductor chip and the first side; and It comprises a first portion disposed below the film substrate, positioned on a plane between the first semiconductor chip and the first side and overlapping with the first conductive film, and a second conductive film positioned between the second semiconductor chip and the second side and having a second portion having a planar area smaller than the planar area of the first portion. The first semiconductor chip has a first long side, a second long side, a first short side, and a second short side, and The first long side and the second long side are opposite to each other in the first direction, and The first short side and the second short side are opposite to each other in a second direction perpendicular to the first direction, and The first long side faces the first side of the film substrate, and The first conductive film is adjacent to one or more of the first long side, the first short side, or the second short side, excluding the second long side, and A film package in which the upper surface of the first conductive film is located at a lower level than the upper surface of the first semiconductor chip.

Description

Film Package {FILM PACKAGE} The present invention relates to a film package. In response to the recent trend of miniaturization, thinning, and lightweighting of electronic products, chip-on-film (hereinafter COF) packaging technology using a flexible film substrate has been proposed. In COF packaging technology, a semiconductor chip is mounted on a film substrate using a flip-chip bonding method and can be connected to an external device via wiring lines. Such COF packages can be applied to portable terminal devices such as cellular phones and PDAs, laptop computers, or panels of display devices. FIG. 1a is a plan view illustrating a film package according to one embodiment of the present invention, FIG. 1b is a bottom view of the film package of FIG. 1a, and FIG. 1c is a cross-sectional view illustrating a cross-section along line II' of FIG. 1a. FIG. 2a is a plan view illustrating a film package according to one embodiment of the present invention, and FIG. 2b is a cross-sectional view illustrating a cross-section along the line II-II' of FIG. 2a. FIG. 3 is a plan view illustrating a film package according to one embodiment of the present invention. FIG. 4 is a plan view illustrating a film package according to one embodiment of the present invention. FIG. 5 is a plan view illustrating a film package according to one embodiment of the present invention. FIG. 6a is a perspective view illustrating a package module including a film package according to one embodiment of the present invention, and FIG. 6b is a cross-sectional view illustrating the usage state of the package module of FIG. 6a. Figure 7 is a layout of a base film including the film packages of Figure 1a. Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings. FIG. 1a is a plan view illustrating a film package (100) according to one embodiment of the present invention, FIG. 1b is a bottom view of the film package (100) of FIG. 1a, and FIG. 1c is a cross-sectional view illustrating a cross-section along the line I-I' of FIG. 1a. Referring to FIGS. 1a to 1c, a film package (100) of one embodiment may include a film substrate (110), a plurality of wiring patterns (120), a first semiconductor chip (131), a second semiconductor chip (132), a first conductive film (151), and a second conductive film (152). According to the embodiment, the film package (100) may further include a protective layer (140). The present invention can effectively improve the heat dissipation characteristics of the film package (100) while reducing manufacturing costs by minimizing the area of the first and second conductive films (151, 152) and by arranging the first conductive film (151) and the second conductive film (152) adjacent to the first semiconductor chip (131), which has relatively high power consumption. In addition, since the first conductive film (151) placed on the mounting surface of the semiconductor chips does not cover the first and second semiconductor chips (131, 132), the process difficulty can be lowered and the yield improved. A film substrate (110) has a first surface (110U) and a second surface (110L) facing in a vertical direction (Z-axis direction), and a first side (110S1) and a second side (110S2) facing in a horizontal direction (Y-axis direction), and the first surface (110U) may include a first region (R1) and a second region (R2) spaced apart in a horizontal direction (or 'first direction') (Y-axis direction). The first surface (110U) is a chip mounting surface on which first and second semiconductor chips (131, 132) are mounted, and the second surface (110L) may be a surface located opposite to it. The first side (110S1) and the second side (110S2) may be sides of a film substrate (110) spaced apart in a direction in which the first and second semiconductor chips (131, 132) are spaced apart or in a direction in which a plurality of wiring patterns (120) are extended. The first region (R1) and the second region (R2) may each be a region in which the first and second semiconductor chips (131, 132) are mounted. According to an embodiment, the first region (R1) and the second region (R2) may each be provided as a plurality of regions corresponding to the number of the first and second semiconductor chips (131, 132). The film substrate (110) may be a flexible film containing polyimide, which is a material with a coefficient of thermal expansion and excellent durability. The material of the film substrate (110) is not limited thereto and may be formed from synthetic resins such as, for example, epoxy resin, acrylic, polyether nitrile, polyether sulfone, polyethylene terephthalate, and polyethylene naphthalate. A plurality of wiring patterns (120) may each include an input pattern (121) extending from a first region (R1) to a first side (110S1) of the film substrate (110), an output pattern (122) extending from a second region (R2) to a second side (110S2) of the film substr