KR-102962953-B1 - A MEMORY DEVICE, A MEMORY CONTROLLER AND A MEMORY SYSTEM INCLUDING THEM

Abstract

A memory system according to an exemplary embodiment of the present disclosure comprises a first memory device configured to include a plurality of first memory blocks each composed of a plurality of first memory cells stacked vertically with respect to a substrate, and a memory controller configured to control the memory operation of the first memory device, wherein the memory controller is configured to select and operate one of heterogeneous control methods for each of the plurality of first memory blocks based on first N/O string information regarding the number of not-open strings (hereinafter referred to as N/O strings) included in each of the plurality of first memory blocks.

Inventors

• 정원택
• 김보창
• 고귀한
• 정재용

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20200812

Claims (20)

1. A first memory device configured to include a plurality of first memory blocks, each composed of a plurality of first memory cells stacked vertically with respect to a substrate; and It includes a memory controller configured to control the memory operation of the first memory device, and The memory controller is configured to select and operate one of heterogeneous control methods for each of the plurality of first memory blocks based on first N/O string information regarding the number of not-open strings (hereinafter, N/O strings) included in each of the plurality of first memory blocks, and A memory system characterized in that the memory controller is configured to provide a first type program command that takes into account the existence of the N/O string to the first memory device when program controlling a first target memory block among the plurality of first memory blocks, wherein the number of the N/O strings is greater than or equal to a threshold value.
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3. In paragraph 1, A memory system characterized by further including control logic configured to detect at least one N/O string from a plurality of strings included in a first target memory block in response to a first type program command, and to convert a plurality of target data to be programmed into a plurality of target memory cells included in the detected at least one N/O string to have a predetermined value for limiting the number of times a program voltage is applied to the plurality of target memory cells.
4. In paragraph 1, A memory system characterized in that the memory controller is configured to provide a second type program command for general program operation to the first memory device during program control for a second target memory block among the plurality of first memory blocks, wherein the number of N/O strings is less than a threshold value.
5. In paragraph 1, A memory system characterized by the memory controller being configured to provide a first type erase command that takes into account the existence of the N/O string during erase control for a first target memory block among the plurality of first memory blocks where the number of N/O strings is greater than or equal to a threshold value, and to provide a second type erase command during erase control for a second target memory block among the plurality of first memory blocks where the number of N/O strings is less than a threshold value.
6. In paragraph 5, A memory system characterized by the above memory device being configured to perform an erase operation on the first target memory block for a first time using a first level erase voltage in response to the first type erase command, and to perform an erase operation on the second target memory block for a second time using a second level erase voltage in response to the second type erase command.
7. In paragraph 6, The above first level is higher than the above second level, and A memory system characterized in that the first time is shorter than the second time.
8. In paragraph 1, A memory system characterized by the memory controller being configured to allocate a first target memory block among a plurality of first memory blocks, wherein the number of N/O strings is greater than or equal to a threshold value, as a first type memory block, and to allocate a second target memory block among a plurality of first memory blocks, wherein the number of N/O strings is less than the threshold value, as a second type memory block that guarantees higher data reliability than the first type memory block.
9. In paragraph 8, The above-mentioned first type memory block is operated as a first level cell, and A memory system characterized in that the above-mentioned second type memory block is operated as a second level cell in which fewer bits than the above-mentioned first level cell are stored.
10. In paragraph 8, The above-mentioned first type memory block is operated to program cold data with an access frequency below a reference value, and A memory system characterized in that the above-mentioned second type memory block is operated to program hot data whose access frequency exceeds the above-mentioned threshold.
11. In paragraph 1, The memory controller is configured to request the first N/O string information from the memory device, and A memory system characterized in that the first memory device is configured to provide the first N/O string information to the memory controller in response to the request.
12. In Paragraph 11, A memory system characterized in that the first N/O string information is stored in some of the memory cells among the plurality of first memory cells or in latches included in the peripheral circuit of the first memory device.
13. In paragraph 1, A memory system characterized in that the memory controller is configured to select and operate one of the heterogeneous control methods for each of the plurality of sub-blocks separated from the plurality of first memory blocks based on the first N/O string information.
14. A memory cell array configured to include a plurality of memory blocks, each composed of a plurality of memory cells stacked vertically with respect to the substrate; and A memory device comprising control logic configured to detect an N/O string for a first target memory block among a plurality of memory blocks in response to a first type program command received from the outside, convert a plurality of target data to be programmed into a plurality of target memory cells included in the detected N/O string to have a predetermined value for limiting the number of times a program voltage is applied, and to perform a general program operation for a second target memory block among the plurality of memory blocks in response to a second type program command received from the outside.
15. In Paragraph 14, The number of N/O strings included in the first target memory block is greater than or equal to a threshold value, and A memory device characterized in that the number of N/O strings included in the second target memory block is less than a threshold value.
16. In Paragraph 14, A memory device characterized in that the first and second type program commands have different patterns.
17. An internal memory configured to store N/O string information regarding the number of Not-Open strings (hereinafter N/O strings) included in each of a plurality of memory blocks included in an external memory device; and A processor configured to determine the number of N/O strings of the plurality of memory blocks based on the N/O string information, and to operate the first target memory blocks containing at least one of the plurality of memory blocks with a first control method, and to operate the second target memory blocks that do not contain the N/O string with a second control method different from the first control method. The above processor is, The above-mentioned first target memory block is operated as a first level cell, and A memory controller characterized by being configured to operate the above-mentioned second target memory block as a second-level cell in which fewer bits than the first-level cell are stored.
18. In Paragraph 17, The above processor is, A first type program command having a first pattern is generated and output to the external memory device such that the program sequence for the first target memory block includes the detection of the N/O string and the conversion of the target memory cells of the detected N/O string. A memory controller characterized by being configured to generate a second type program command having a second pattern to normally proceed the program sequence for the second target memory block and output it to the external memory device.
19. In Paragraph 17, The above processor is, A first type erase command having a first pattern is generated and output to the external memory device such that an erase operation for the first target memory block is performed for a first time at a first level erase voltage, and A memory controller characterized by being configured to generate and output externally a second type erase command having a second pattern such that an erase operation for the second target memory block is performed for a second time longer than the first time at a second level erase voltage lower than the first level.
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Description

A memory device, a memory controller, and a memory system including them The technical concept of the present disclosure relates to a memory device, and more specifically, to a memory device including at least one not-open string, a controller for controlling the memory device, and a memory system including the same. With the recent advancement of data technology, there is a growing demand for 3D memory devices with high integration density as vast amounts of data must be stored with high reliability. However, in 3D memory devices, not-open strings (or off-strings) where channels are not formed may occur due to manufacturing errors. Since it is difficult to program data into memory cells with not-open strings and these not-open strings negatively affect surrounding memory cells, technology to resolve this issue is currently required. FIG. 1 is a block diagram showing a memory system according to an exemplary embodiment of the present disclosure. FIG. 2 is a drawing for explaining the operation of a memory system according to an exemplary embodiment of the present disclosure. FIGS. 3a and FIGS. 3b are flowcharts for specifically describing embodiments of step S130 of FIGS. 2. FIGS. 4a to 4c are drawings for specifically describing the operation of the first type command and the second type command of FIG. 3a. FIG. 5a is a block diagram showing a memory cell array of FIG. 1, FIG. 5b is a first example of a perspective cross-sectional view of a memory cell array of FIG. 1, and FIG. 5c is a second example of a perspective cross-sectional view of a memory cell array of FIG. 1. FIG. 6 is a drawing for explaining a C2C (Chip to Chip) structure applied to a memory device according to an exemplary embodiment of the present disclosure. FIG. 7 is a flowchart for specifically explaining the operation of a memory device in response to the first type program command of FIG. 4a. FIGS. 8a to 8c are drawings for explaining the operation method of a memory device in response to the first type program command of FIG. 4a. FIG. 9 is a flowchart for specifically explaining step S210 of FIG. 7. FIGS. 10a to 10c are drawings for explaining the operation method of a memory device in response to the first and second type erase commands of FIG. 4a. FIGS. 11a and FIGS. 11b are drawings for specifically explaining the first and second type memory blocks of FIG. 3b. FIGS. 12a to 12c are drawings for specifically describing an embodiment in which one of the heterogeneous control methods for each of the sub-blocks included in the memory block is selected and operated. FIG. 13 is a flowchart for explaining the operation method of a memory controller according to an exemplary embodiment of the present disclosure. FIG. 14 is a block diagram showing a memory system according to an exemplary embodiment of the present disclosure. FIG. 15 is a table diagram exemplarily showing the N/O string information of FIG. 14. FIG. 16 is a flowchart for explaining the operation method of a memory controller according to an exemplary embodiment of the present disclosure. FIGS. 17a and FIGS. 17b are drawings for specifically describing the first and second type memory devices of FIG. 16. FIG. 18 is a block diagram showing a test system for generating N/O string information according to an exemplary embodiment of the present disclosure. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. Hereinafter, embodiments of the present disclosure may be described with reference to NAND flash memory, in particular, vertical NAND flash memory. However, the technical concept of the present disclosure is not limited to NAND flash memory. The technical concept of the present disclosure may be applied to various non-volatile memory devices such as EEPROM (Electrically Erasable and Programmable ROM), NOR flash memory devices, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), etc. Meanwhile, a memory device may be referred to as a memory chip. FIG. 1 is a block diagram showing a memory system (100) according to an exemplary embodiment of the present disclosure, and FIG. 2 is a diagram for explaining the operation of a memory system (100) according to an exemplary embodiment of the present disclosure. Referring to FIG. 1, the memory system (10) may include a memory controller (100) and a memory device (200). The memory controller (100) may include a processor (110) and an internal memory (120). The processor (110) may control the overall operation of the memory system (10) including the memory controller (100) and control memory operations such as program (or write), read, or erase operations of the memory device (200). The internal memory (120) may store Not-Open string (hereinafter N/O string) information (122) that serves as a basis for performing operations according to exemplary embodiments of the present disclosure. Specific details regarding the N/O string are