KR-102962954-B1 - A PHASE LOCKED LOOP AND ELECTRONIC APPARATUS

Abstract

An electronic device according to an exemplary embodiment of the present disclosure includes a phase-locked loop configured to perform a two-point modulation operation using a first and a second modulation path for a data signal, wherein the phase-locked loop is configured to generate a gain based on the derivative of a first phase error signal generated in the first modulation path to adjust the frequency change amount of the data signal through the second modulation path to correspond to the frequency change amount of the data signal through the first modulation path.

Inventors

• 김신웅
• 김명균
• 이준희
• 한상욱

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20200907

Claims (10)

1. In electronic devices, It includes a phase-locked loop configured to perform a two-point modulation operation using first and second modulation paths for a data signal, and The above phase-locked loop is, A gain for adjusting the frequency change amount of the data signal through the second modulation path to correspond to the frequency change amount of the data signal through the first modulation path is configured to be generated based on the derivative value of the first phase error signal generated in the first modulation path, and The above phase-locked loop is, It includes a gain calibrator configured to generate a derivative value of the first phase error signal from the first phase error signal received from the first modulation path, generate a delta gain based on the derivative value, and generate the gain by accumulating the delta gain. The above gain corrector is, An electronic device characterized by being configured to check whether the derivative value is included in a reference range and to scale the delta gain based on the check result.
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3. In paragraph 1, The above gain corrector is, An electronic device characterized by being configured to generate the delta gain having a magnitude proportional to the magnitude of the derivative value.
4. In paragraph 1, The above gain corrector is, An electronic device characterized by being configured to generate the derivative value in accordance with the level transition timing of the data signal.
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6. In paragraph 1, The above gain corrector is, An electronic device characterized by scaling the delta gain by a predetermined ratio when the derivative value is included in a reference range.
7. In paragraph 1, The above gain corrector is, An electronic device characterized by being configured to generate a second phase error signal from a test data signal for a predetermined period of time and to set a reference range based on the maximum and minimum values of the second phase error signal.
8. In paragraph 1, The above gain corrector is, An electronic device characterized by being configured to filter the high-frequency component of the first phase error signal before generating the derivative value.
9. In the method of operating an electronic device, A step of applying a data signal to the low-pass and high-pass modulation paths of a phase-locked loop; A step of generating a derivative value from a phase error signal generated from the above low-pass modulation path; A step of generating a gain to adjust the frequency change amount of the data signal through the high-pass modulation path based on the derivative value; and The method includes the step of performing two-point modulation on the data signal based on the gain through the low-pass and high-pass modulation paths. The step of generating the above gain is, A step of generating a delta gain based on the above derivative value; and It includes the step of accumulating the delta gain to generate the above gain, The step of generating the above delta gain is, A step of checking whether the above derivative value is included within a reference range; and A method of operating an electronic device characterized by including a step of scaling the delta gain based on the above verification result.
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Description

A Phase Locked Loop and Electronic Apparatus Including the Same The technical concept of the present disclosure relates to an electronic device, and more specifically, to a phase-locked loop configured to perform a two-point modulation operation and an electronic device including the same. A phase-locked loop is a circuit generally used to adjust the frequency and/or phase of an oscillator, and the phase-locked loop can be used to lock the frequency and/or phase of the oscillator to a reference frequency signal having an accurate frequency. In some applications, a phase-locked loop can be used to modulate the frequency and/or phase of an oscillator using a data signal. With technological advancements, phase-locked loops can support two-point modulation techniques to modulate data signals with wide bandwidths. Two-point modulation involves performing modulation of the data signal using two modulation paths included in the phase-locked loop. However, mismatches in the frequency variation of the data signal may occur between the two modulation paths. Since such mismatches negatively affect the performance of the phase-locked loop, a structure and method are required to find an effective gain applied to a specific modulation path to resolve this issue. FIG. 1 is a block diagram showing a phase-locked loop according to an exemplary embodiment of the present disclosure. FIG. 2 is a block diagram specifically illustrating a phase-locked loop according to an exemplary embodiment of the present disclosure. FIG. 3 is a block diagram showing a gain corrector according to an exemplary embodiment of the present disclosure. Figures 4 and 5 are diagrams for explaining the operation of the gain corrector of Figure 3. FIG. 6 is a block diagram showing a gain corrector according to an exemplary embodiment of the present disclosure. FIGS. 7a and 7b are block diagrams illustrating a gain corrector according to an exemplary embodiment of the present disclosure. FIGS. 8A and FIGS. 8B are diagrams for explaining the operation method of the gain corrector of FIG. 7A. FIG. 9 is a block diagram showing a gain corrector according to an exemplary embodiment of the present disclosure. FIG. 10 is a block diagram showing an electronic device using a phase-locked loop according to exemplary embodiments of the present disclosure. FIG. 11 is a block diagram showing a communication device according to an exemplary embodiment of the present disclosure. FIG. 12 is a drawing showing communication devices including a phase-locked loop according to one embodiment of the present disclosure. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. FIG. 1 is a block diagram showing a phase-locked loop (100) according to an exemplary embodiment of the present disclosure. Referring to FIG. 1, the phase-locked loop (100) may include first and second modulation paths (110, 120), a gain corrector (130), a summer (140), and an oscillator (150). The phase-locked loop (100) according to an exemplary embodiment of the present disclosure may perform two-point modulation on a data signal (DS) using the first and second modulation paths (110, 120) and adaptively perform matching of frequency change amounts between the first and second modulation paths (110, 1120). Two-point modulation may also be referred to as dual-port modulation. In some embodiments, the first modulation path (110) may be a low-pass modulation path and the second modulation path (120) may be a high-pass modulation path. However, it is clear that this is an exemplary embodiment and the technical concept of the present disclosure is not limited thereto. In an exemplary embodiment, the first modulation path (110) may receive an output signal (or, output frequency signal) (Fout), a reference frequency signal (Fref), and a data signal (DS) output from an oscillator (150). The first modulation path (110) may generate a first control signal (Cntl_1) based on the output signal (Fout), the reference frequency signal (Fref), and the data signal (DS). For example, the first modulation path (110) may divide the output signal (Fout) by a division ratio corresponding to the data signal (DS) and the center frequency of a selected channel, and generate a phase error signal (PES) by comparing the divided signal with the reference frequency signal (Fref). The first modulation path (110) may generate a first control signal (Cntl_1) based on the phase error signal (PES). A specific configuration example of the first modulation path (110) is described in FIG. 2. Meanwhile, the second modulation path (120) can receive a data signal (DS) and perform a modulation operation on the data signal (DS). For ease of understanding, the oscillator (150) is depicted as not being included in the second modulation path (120), but the second modulation path (120) may be a concept that includes the oscillator (150). At this time, the first frequency change amount of