KR-102962955-B1 - APPARATUSE FOR PHASE LOCKING LOOP AND METHOD OF OPERATING THE PHASE LOCKING LOOP

Abstract

The phase locking device of the present disclosure may include a frequency modulation circuit that outputs a reference signal multiplied by a certain ratio from the frequency of the input signal based on an input signal, a sigma-delta modulator that outputs division ratio information regarding one of a plurality of division ratios a number of times proportional to the frequency of the reference signal, and a phase locking loop (PLL) circuit that performs a fractional division-based phase locking operation based on the reference signal and the division ratio information.

Inventors

• 정우철
• 이용선

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20200921

Claims (10)

1. A frequency modulation circuit that, in response to a first activation command, outputs a reference signal that is multiplied by a certain ratio from the frequency of the input signal based on the input signal and has reduced random noise compared to the input signal; A sigma-delta modulator that outputs division rate information regarding one of a plurality of division rates a number of times proportional to the frequency of the reference signal; and A phase locking loop (PLL) circuit that performs a fractional division-based phase locking operation in response to a second activation command, based on the reference signal and the division ratio information. A phase fixing device including
2. In paragraph 1, The above phase-locked loop circuit is, A divider that provides a feedback signal having a frequency obtained by dividing the frequency of the output signal by the division ratio to the input of the phase-locked loop circuit. A phase fixing device characterized by including
3. In paragraph 2, The above phase-locked loop circuit is, A phase-frequency detector that detects the phase difference between the feedback signal and the reference signal and outputs the detection result Includes, A phase fixing device characterized by generating a phase-fixed output signal corresponding to the reference signal based on the above detection result.
4. In paragraph 2, The above sigma-delta modulator is, A phase locking device characterized by outputting the division ratio information in response to a change in the logic state of the reference signal.
5. In paragraph 1, The above frequency modulation circuit is, A divider that outputs a feedback signal in which the logic state changes in response to detecting a certain number of edge changes of the output signal; A mode selection circuit that outputs a selection signal regarding whether to output a delay indication signal based on the above feedback signal; A multiplexer (MUX) that determines whether to output a delay indication signal based on the above selection signal; and A delay circuit that delays the output of the input signal in response to the input of the above delay indication signal. A phase fixing device characterized by including
6. In paragraph 1, The above frequency modulation circuit is, A pulse generator that fixes the phase of an oscillator by applying a pulse signal to an oscillator that generates the reference signal based on the input signal. A phase fixing device characterized by including
7. In paragraph 1, A controller device that outputs a command signal including the first activation command and the second activation command based on an operation mode A phase fixing device characterized by further including
8. In Paragraph 7, The above controller device is, A phase locking device characterized by outputting the first activation command to the frequency modulation circuit in response to the case where the above operation mode is an operation standby mode, and blocking the output of the second activation command to the phase locking loop circuit.
9. In the method of operating a phase fixing device, A step of receiving a command signal including a first activation command and a second activation command; A step of generating a reference signal multiplied by a certain ratio from the frequency of the input signal based on the input signal in response to the first activation command; A step of outputting division rate information regarding one of a plurality of division rates a number of times proportional to the frequency of the reference signal; and A step of performing a fractional division-based phase locking operation in response to the second activation command above, based on the reference signal and the division ratio information. A method of operation of a phase-locking device including
10. A controller device that generates a command signal including a first activation command and a second activation command based on an operation mode; and A phase fixing device that receives the command signal, generates a reference signal multiplied by a certain ratio from the frequency of the input signal based on the input signal in response to the first activation command, generates division ratio information regarding one of a plurality of division ratios a number of times proportional to the frequency of the reference signal, and performs a fractional division-based phase fixing operation based on the reference signal and the division ratio information in response to the second activation command; A phase-locked system including

Description

Phase Locking Loop Apparatus and Method of Operating the Phase Locking Loop The technical concept of the present disclosure relates to a phase-locked loop, and more specifically, to a phase-locking device and a method of operating the phase-locking device. A PLL circuit or a clock generator equipped with a PLL circuit can generate a phase-locked clock signal. For example, the clock signal can be used to transmit data from a transmitter or to recover data from a receiver. In this case, the PLL circuit can be classified into a ring-PLL circuit, an LC (inductor-capacitor)-PLL circuit, etc. Recently, PLL circuits have adopted a technique to fix the clock phase through subsampling to improve noise characteristics. However, since the frequency divider does not divide the clock during subsampling, there were limitations in performing fractional division. To overcome these limitations, a technique utilizing a Digital-to-Time Converter (DTC) was introduced to enable fractional division during subsampling; however, this resulted in performance degradation of the clock generator due to limited resolution and quantization noise. FIG. 1 is a block diagram illustrating the configuration of a phase fixing system including a phase fixing device and a controller device according to an embodiment of the present disclosure. FIG. 2a is a graph illustrating the logic of the clock signal and reference signal of a voltage-controlled oscillator according to one embodiment, and FIG. 2b is a graph showing an example of generating a fractional division ratio to perform a fractional division-based phase lock operation. FIG. 3 is a block diagram illustrating a phase-locked loop circuit according to one embodiment. FIG. 4 is a block diagram illustrating a frequency modulation circuit according to one embodiment, and FIG. 5 is a block diagram illustrating a frequency modulation circuit according to another embodiment. FIG. 6a is a graph showing division ratio information according to a comparative example, and FIG. 6b is a graph showing division ratio information output based on a reference signal according to FIG. 4 or FIG. 5. FIG. 7 is a graph showing the noise power of a reference signal output by a comparative example, and FIG. 8 is a graph showing the noise power of a reference signal output by an embodiment of the present disclosure. FIG. 9 is a comparison graph showing the fixed time of a phase-locked loop circuit according to one embodiment. FIG. 10 is a flowchart illustrating the operation method of a phase fixing device according to one embodiment. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. FIG. 1 is a block diagram illustrating the configuration of a phase fixing system including a phase fixing device (10) and a controller device (20) according to an embodiment of the present disclosure. Referring to FIG. 1, a phase locking system may include a phase locking device (10) and a controller device (20), and based on a command from the controller device (20), the phase locking device (10) may generate an output signal (OUT) from an input signal (IN). The phase locking device (10) may include a frequency modulation circuit (11), a sigma-delta modulator (12), and a phase locking loop circuit (13). A phase locking device (10) according to one embodiment receives an input signal (IN) and can generate a reference signal (REF) in a frequency modulation circuit (11) based on the input signal (IN). The frequency modulation circuit (11) can provide the generated reference signal (REF) to a phase locking loop circuit (13) and a sigma-delta modulator (12), and based on the clock period of the reference signal (REF), the sigma-delta modulator (12) can generate division ratio information (DR), and the phase locking loop circuit (13) can generate an output signal (OUT). The frequency modulation circuit (11) can generate a reference signal (REF) based on the frequency of the input signal (IN), and, for example, can generate a reference signal (REF) that doubles the frequency of the input signal (IN) by a certain ratio. The frequency modulation circuit (11) can output a signal having a high-frequency noise cutoff bandwidth as the reference signal (REF). The frequency modulation circuit (11) can be, for example, a Multiplying Delay Locking Loop (MDLL) or an Injection Phase Locking Loop (Injection PLL), and since jitter components are not accumulated, the ratio of random noise (RJ) of the internal oscillator can be significantly reduced. Therefore, the frequency modulation circuit (11) can output a reference signal (REF) with low noise even when receiving an input signal (IN) containing noise, and the reference signal (REF) can have a high-frequency noise cutoff bandwidth. The sigma-delta modulator (12) receives a reference signal (REF) from the frequency modulation circuit (11) and can output a division ratio information (DR) in proportion to the frequency of the reference