KR-102962956-B1 - SEMICONDUCTOR PACKAGE

Abstract

The technical concept of the present invention comprises: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip; an underfill material layer between the first semiconductor chip and the second semiconductor chip; and a first dam structure provided on the first semiconductor chip, extending along the edge of the second semiconductor chip and including unit dam structures spaced apart from each other with a slit in between; wherein the level of the upper surface of the first dam structure is between the level of the lower surface of the second semiconductor chip and the level of the upper surface of the second semiconductor chip, and the unit dam structures of the first dam structure each have a rectangular shape in a planar view, and the first side wall of the first dam structure contacts the underfill material layer, and the facing

Inventors

• 이형주
• 강운병
• 박세철
• 박상식
• 윤효진
• 이택훈
• 최주일

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20210712

Claims (20)

1. A first semiconductor substrate, a first semiconductor device layer provided on the first semiconductor substrate and including a first wiring structure, and a first semiconductor chip including a first through electrode penetrating the first semiconductor substrate and electrically connected to the first wiring structure; A second semiconductor chip stacked on the upper surface of the first semiconductor chip; An underfill material layer between the first semiconductor chip and the second semiconductor chip; and A first dam structure comprising unit dam structures provided on the upper surface of the first semiconductor chip, extending along the edge of the second semiconductor chip, and spaced apart from each other with a slit in between; Includes, The level of the upper surface of the first dam structure is between the level of the lower surface of the second semiconductor chip and the level of the upper surface of the second semiconductor chip, and The unit dam structures of the first dam structure each have a rectangular shape in a planar view, The first side wall of the first dam structure is in contact with the underfill material layer and includes a plane parallel to the side wall of the facing second semiconductor chip, The above unit dam structures include a plurality of first unit dam structures adjacent in a first direction, and the width of the slit in the first direction between the first unit dam structures is 100% or less of the horizontal width of each of the first unit dam structures along the first direction, and The first unit dam structures are spaced apart from the sidewall of the second semiconductor chip in a second direction, and the second direction is different from the first direction of the semiconductor package.
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3. In Article 1, A semiconductor package in which the horizontal width of each of the unit dam structures of the first dam structure is between 30㎛ and 150㎛.
4. In Article 1, The above-mentioned first dam structure is a semiconductor package containing metal.
5. In Article 1, The above-mentioned first dam structure is a semiconductor package comprising a polymer.
6. In Article 1, The above underfill material layer is, A linear sidewall that contacts the first sidewall of the first dam structure and extends in a direction perpendicular to the upper surface of the first semiconductor chip; and A curvilinear sidewall connected to the linear sidewall above; Includes, The above-described curved sidewall defines an indentation extending along the edge of the second semiconductor chip in a semiconductor package.
7. In Article 6, The upper surface of the first dam structure is a semiconductor package continuously connected to the curved sidewall of the underfill material layer.
8. In Article 1, A semiconductor package further comprising a molding layer provided on the first semiconductor chip and planarly surrounding the second semiconductor chip.
9. In Article 8, The first dam structure is a semiconductor package exposed to the side wall of the molding layer.
10. In Article 1, The first semiconductor chip includes a trench filled with the underfill material layer, and The trench of the first semiconductor chip is a semiconductor package provided between the first sidewall of the first dam structure and the edge of the second semiconductor chip.
11. In Article 1, The above-mentioned first dam structure is, A first unit dam structure having a first horizontal width in a direction parallel to the edge of the second semiconductor chip; and A second unit dam structure having a second horizontal width greater than the first horizontal width in a direction parallel to the edge of the second semiconductor chip; A semiconductor package including
12. In Article 1, A semiconductor package further comprising a second dam structure provided on the first semiconductor chip and spaced apart from the edge of the second semiconductor chip with the first dam structure in between.
13. In Article 1, A semiconductor package further comprising a plurality of semiconductor chips stacked on the second semiconductor chip and stacked together in a vertical direction.
14. First semiconductor chip; A second semiconductor chip stacked on the upper surface of the first semiconductor chip; and An underfill material layer provided between the first semiconductor chip and the second semiconductor chip, covering at least a portion of the sidewall of the second semiconductor chip; Includes, The above underfill material layer includes a lower sidewall linearly extended in a direction perpendicular to the upper surface of the first semiconductor chip and a curved upper sidewall connected to the lower sidewall, and A semiconductor package in which the upper sidewall of the underfill material layer defines a groove provided in the outer region of the underfill material layer.
15. In Article 14, The groove in the above underfill material layer is a semiconductor package that is linearly extended along the edge of the second semiconductor chip.
16. In Article 14, A semiconductor package further comprising a first dam structure provided on the upper surface of the first semiconductor chip and in contact with the lower sidewall of the underfill material layer.
17. In Article 16, The upper surface of the first dam structure is continuously connected to the upper side wall, and At the boundary between the upper surface and the upper side wall of the first dam structure, the inclination of the upper surface of the first dam structure and the inclination of the upper side wall are the same semiconductor package.
18. In Article 16, The first dam structure is in the form of a bar extending along the edge of the second semiconductor chip, and The above-mentioned first dam structure includes a plurality of slits, and A semiconductor package in which the first side wall of the first dam structure contacts the lower side wall of the underfill material layer and includes a plane parallel to the side wall of the facing second semiconductor chip.
19. In Article 16, The above-mentioned first dam structure is a semiconductor package comprising a photoresist material.
20. A first semiconductor substrate, a first semiconductor device layer provided on the first semiconductor substrate and including a first wiring structure, and a first semiconductor chip including a first through electrode penetrating the first semiconductor substrate and electrically connected to the first wiring structure; A second semiconductor chip provided on the first semiconductor chip, comprising a second semiconductor substrate, a second semiconductor device layer provided on the second semiconductor substrate and including a second wiring structure, and a second through electrode penetrating the second semiconductor substrate and electrically connected to the second wiring structure; A connection bump provided between the first semiconductor chip and the second semiconductor chip; An underfill material layer provided between the first semiconductor chip and the second semiconductor chip, surrounding the sidewall of the connection bump, and covering at least a portion of the sidewall of the second semiconductor chip; A first dam structure provided on the first semiconductor chip, in contact with the underfill material layer, extending along the edge of the second semiconductor chip, and comprising a plurality of slits and a plurality of unit dam structures spaced apart by the plurality of slits; and A molding layer provided on the first semiconductor chip and covering the underfill material layer and the first dam structure; Includes, The above-mentioned first dam structure is, A first sidewall having a plane parallel to the sidewall of the facing second semiconductor chip and in contact with the underfill material layer; and An upper surface having a level between the level of the lower surface of the second semiconductor chip and the level of the upper surface of the second semiconductor chip; Includes, A semiconductor package in which the spacing between adjacent unit dam structures in a first direction among the plurality of unit dam structures is 100% or less of the horizontal width according to the first direction of each of the plurality of unit dam structures.

Description

Semiconductor Package {SEMICONDUCTOR PACKAGE} The technical concept of the present invention relates to a semiconductor package, and more specifically, to a semiconductor package comprising an underfill material layer. Recently, the demand for portable devices in the electronics market has been rapidly increasing, leading to a continuous demand for the miniaturization and lightweighting of electronic components mounted on these products, such as semiconductor chips. To achieve this miniaturization and lightweighting of electronic components, not only is technology required to reduce the individual size of the mounted components, but also semiconductor packaging technology is needed to integrate multiple semiconductor chips constituting the components into a single package. FIG. 1a is a cross-sectional view of a semiconductor package according to exemplary embodiments of the present invention. Figure 1b is a planar perspective view of the semiconductor package of Figure 1a. Figure 1c is an enlarged view showing the part labeled "1C" in Figure 1a. FIGS. 2a to 2g are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments of the present invention. FIG. 3a is a cross-sectional view of a semiconductor package according to exemplary embodiments of the present invention. Figure 3b is a planar perspective view of the semiconductor package of Figure 3a. FIG. 4a is a cross-sectional view of a semiconductor package according to exemplary embodiments of the present invention. Figure 4b is an enlarged view showing the part labeled "4B" in Figure 4a. FIGS. 5a to 5c are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments of the present invention. FIG. 6 is a cross-sectional view of a semiconductor package according to exemplary embodiments of the present invention. FIG. 7 is a cross-sectional view of a semiconductor package according to exemplary embodiments of the present invention. FIG. 8 is a cross-sectional view of a semiconductor package according to exemplary embodiments of the present invention. FIG. 9 is a planar perspective view of a semiconductor package according to exemplary embodiments of the present invention. FIGS. 10a and FIGS. 10b are planar perspective views of a semiconductor package according to exemplary embodiments of the present invention. FIG. 11 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. FIG. 1a is a cross-sectional view of a semiconductor package (10) according to exemplary embodiments of the present invention. FIG. 1b is a planar perspective view of the semiconductor package (10) of FIG. 1a. FIG. 1c is an enlarged view showing the portion marked "1C" in FIG. 1a. Referring to FIGS. 1a through 1c, the semiconductor package (10) may include a first semiconductor chip (100) and a second semiconductor chip (200), a third semiconductor chip (300), a fourth semiconductor chip (400), and a fifth semiconductor chip (500) stacked vertically on the first semiconductor chip (100). The planar area of the first semiconductor chip (100) may be larger than the planar area of the second semiconductor chip (200) stacked on the upper surface (161) of the first semiconductor chip (100), and the planar areas of the third to fifth semiconductor chips (300, 400, 500) may be generally the same as the planar area of the second semiconductor chip (200). In the following, a direction parallel to the upper surface (161) of the first semiconductor chip (100) is defined as a horizontal direction (e.g., X direction and/or Y direction), and a direction perpendicular to the upper surface (161) of the first semiconductor chip (100) is defined as a vertical direction (e.g., Z direction). Additionally, in this specification, a horizontal distance or horizontal width refers to a length along the horizontal direction (e.g., X direction and/or Y direction), and a vertical level refers to a level along the vertical direction (e.g., Z direction). The first to fifth semiconductor chips (100, 200, 300, 400, 500) may be electrically connected to each other through the second to fifth connecting bumps (270, 370, 470, 570) or electrically connected to the first semiconductor chip (100). Additionally, the first to fifth semiconductor chips (100, 200, 300, 400, 500) may be attached to each other by an underfill material layer. In the present specification, an underfill material layer disposed between a first semiconductor chip (100) and a second semiconductor chip (200) is referred to as a first underfill material layer (630), an underfill material layer disposed betwe