KR-102962958-B1 - Page buffer including a plurality of latches and Memory device having the same

Abstract

A page buffer comprising a plurality of latches and a memory device having the same are disclosed. A memory device according to one aspect of the technical concept of the present disclosure comprises a memory cell array comprising a plurality of memory cells and a page buffer connected to the memory cell array through a plurality of bit lines and connected to each bit line, wherein the page buffer comprises a page buffer circuit comprising N data latches for storing data to be programmed and at least one additional latch, and a control logic for controlling a setting for the page buffer, wherein, according to a first setting for the page buffer, data to be programmed in a current program operation is stored in some of the N data latches and the additional latch, and data to be programmed in a next program operation before the current program operation is completed is stored in other of the N data latches and the additional latch, and according to a second setting for the page buffer, data provided from an external source is not stored in the additional latch during the current program operation and the next program operation.

Inventors

• 정기호
• 남상완
• 김형곤

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20211022

Claims (13)

1. A memory cell array comprising a plurality of memory cells; A page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each bit line, wherein the page buffer includes N data latches storing data to be programmed and at least one additional latch (wherein N is an integer greater than or equal to 2); and Control logic for controlling the settings for the page buffer based on setting information; and According to the first setting for the page buffer above, data programmed in the current program operation is stored in some of the N data latches and the additional latches, and data to be programmed in the next program operation before the current program operation is completed is stored in some of the remaining N data latches and the additional latches. A memory device characterized in that, according to a second setting for the page buffer, data provided from the outside is not stored in the additional latch during the current program operation and the next program operation.
2. In paragraph 1, Each of the above plurality of memory cells is a Triple Level Cell (TLC) that stores 3 bits of data, and the N data latches include 3 data latches, and A memory device characterized in that 3 bits of data programmed in the current program operation and 1 bit of data among 3 bits of data to be programmed in the next program operation are stored in the three data latches and the additional latch.
3. In paragraph 2, A memory device characterized in that, as the programming of one bit of the three bits of data programmed in the current program operation is completed, another one bit of the three bits of data to be programmed in the next program operation is provided and stored in the page buffer before the current program operation is completed.
4. In paragraph 3, A memory device characterized in that, as the programming of another bit of the 3 bits of data programmed in the current program operation is completed, the remaining 1 bit of the 3 bits of data to be programmed in the next program operation is provided and stored in the page buffer before the current program operation is completed.
5. In paragraph 1, The above memory device further comprises a ready/busy signal generating circuit that outputs a ready/busy signal, and A memory device characterized by receiving data to be programmed in the next program operation by outputting the ready/busy signal indicating ready immediately after the current program operation starts.
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10. In paragraph 1, The above page buffer includes a plurality of additional latches, and A memory device characterized by the fact that data programmed in the current program operation and data of two or more bits to be programmed in the next program operation are stored together in the page buffer.
11. A memory cell array comprising a plurality of memory cells; A page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each bit line, wherein the page buffer includes N data latches storing data to be programmed and at least one additional latch (wherein N is an integer greater than or equal to 2); and Control logic for controlling the settings for the above page buffer; provided, According to the first setting for the page buffer above, data programmed in the current program operation is stored in some of the N data latches and the additional latches, and data to be programmed in the next program operation before the current program operation is completed is stored in other of the N data latches and the additional latches. According to the second setting for the above page buffer, in the current program operation and the next program operation, data provided from the outside is not stored in the additional latch, and The above page buffer further includes a sensing latch related to data sensing, and A memory device characterized in that, according to the second setting above, the additional latch is connected to the bitline through a sensing node to sense data stored in a memory cell.
12. A memory cell array comprising a plurality of memory cells; A page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each bit line, wherein the page buffer includes N data latches storing data to be programmed and at least one additional latch (wherein N is an integer greater than or equal to 2); and Control logic for controlling the settings for the above page buffer; provided, According to the first setting for the page buffer above, data programmed in the current program operation is stored in some of the N data latches and the additional latches, and data to be programmed in the next program operation before the current program operation is completed is stored in other of the N data latches and the additional latches. According to the second setting for the above page buffer, in the current program operation and the next program operation, data provided from the outside is not stored in the additional latch, and The above page buffer further includes a forcing latch that controls the precharge voltage level of the bit line, and According to the second setting above, the additional latch stores a value related to the adjustment of the precharge voltage level of the bit line, and A memory device characterized in that the precharge voltage level of the bitline varies based on the value stored in the forcing latch and the additional latch.
13. A memory cell array comprising a plurality of memory cells; A page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each bit line, wherein the page buffer includes N data latches storing data to be programmed and at least one additional latch (wherein N is an integer greater than or equal to 2); and Control logic for controlling the settings for the above page buffer; provided, According to the first setting for the page buffer above, data programmed in the current program operation is stored in some of the N data latches and the additional latches, and data to be programmed in the next program operation before the current program operation is completed is stored in other of the N data latches and the additional latches. According to the second setting for the above page buffer, in the current program operation and the next program operation, data provided from the outside is not stored in the additional latch, and According to the second setting above, the additional latch stores information indicating whether the data programmed in the current program operation is a program path, and A memory device characterized in that data programmed in the current program operation is maintained in the page buffer until the current program operation is completed.

Description

Page buffer including a plurality of latches and Memory device having the same The technical concept of the present disclosure relates to a memory device, and more specifically, to a page buffer comprising a plurality of latches and a memory device having the same. Recently, with the multi-functionalization of information and communication devices, there is a demand for larger capacity and higher integration of memory devices. A memory device may include a page buffer connected to each bit line of memory cells to store data in memory cells or output data from memory cells, and the page buffer may include one or more latches. A page buffer may be equipped with multiple latches, including latches for temporarily storing written data and latches for sensing data. However, there may be limitations in improving various functions of the memory device by efficiently utilizing the multiple latches provided in the page buffer. FIG. 1 is a block diagram showing a memory device according to one embodiment of the present disclosure. Figure 2 is a diagram schematically showing the structure of the memory device of Figure 1. FIG. 3 is a drawing illustrating an exemplary memory cell array of FIG. 1 according to one embodiment of the present disclosure. FIG. 4 is a perspective view showing the memory block of FIG. 3 according to one embodiment of the present disclosure. FIG. 5 is a drawing showing a page buffer according to an exemplary embodiment of the present disclosure. FIG. 6 is a flowchart illustrating a method of operation of a memory device according to an exemplary embodiment of the present disclosure. FIGS. 7a and 7b are drawings illustrating an example of operation when an additional latch in an embodiment of the present disclosure is used for cache purposes. FIG. 8 is a diagram showing an example of operation in which an additional latch in an embodiment of the present disclosure is used for sensing/forcing purposes. Figures 9 and 10 are drawings illustrating examples of operation when an additional latch is used for forging purposes. FIG. 11 is a diagram illustrating an example of operation in which an additional latch in an embodiment of the present disclosure is used for data retention purposes. FIGS. 12a and 12b are diagrams illustrating examples of the operation of a memory device when an additional latch is used for data retention. FIG. 13 is a block diagram showing a memory device according to an exemplary embodiment of the present disclosure. FIGS. 14a through 14g are drawings illustrating an example in which a page buffer has a plurality of additional latches according to an exemplary embodiment of the present disclosure. FIG. 15 is a block diagram showing a memory system according to an exemplary embodiment of the present disclosure. FIG. 16 is a block diagram showing an example of applying a memory device according to embodiments of the present disclosure to an SSD system. Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. FIG. 1 is a block diagram showing a memory device (10) according to one embodiment of the present disclosure. Referring to FIG. 1, the memory device (10) may include a memory cell array (100) and a peripheral circuit (200), and the peripheral circuit (200) may include a page buffer circuit (210), control logic (220), a voltage generator (230), and a row decoder (240). Although not shown in FIG. 1, the peripheral circuit (200) may further include various components such as a data input/output circuit, column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc. A memory cell array (100) may be connected to a page buffer circuit (210) via bit lines (BL) and to a row decoder (240) via word lines (WL), string select lines (SSL), and ground select lines (GSL). The memory cell array (100) may include a plurality of memory cells, for example, the memory cells may be flash memory cells. Hereinafter, embodiments of the present disclosure will be described in detail with the example of a case where the plurality of memory cells are NAND flash memory cells. However, the present invention is not limited thereto, and in some embodiments, the plurality of memory cells may be resistive memory cells such as ReRAM (resistive RAM), PRAM (phase change RAM), FRAM (ferroelectric RAM), or MRAM (magnetic RAM). The control logic (220) can output various control signals, such as a voltage control signal (CTRL_vol), a row address (X-ADD), and a column address (Y-ADD), for writing or programming data to the memory cell array (100), reading data from the memory cell array (100), or erasing data stored in the memory cell array (100), based on a command (CMD), an address (ADD), and a control signal (CTRL). By doing so, the control logic (220) can control various operations within the memory device (10) overall. The voltage generator (230) can generate various types of voltages for performing program, read, and