KR-102962960-B1 - Non-volatile Memory Device

Abstract

A non-volatile memory device comprises word lines stacked along a vertical direction on the upper surface of a substrate, erase control lines spaced apart from each other in a first direction and each extended in a second direction, a pass transistor circuit including a first pass transistor connected to a first group including erase control lines relatively close to a word line cut area and a second pass transistor connected to a second group including erase control lines relatively far from a word line cut area, and a memory cell array including a plurality of blocks, wherein each block includes a plurality of channel structures connected to the word lines and erase control lines and each extended in a vertical direction.

Inventors

• 박상원
• 임봉순
• 김병수

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20211018

Claims (20)

1. Multiple word lines stacked along a vertical direction on the upper surface of the substrate; A plurality of erase control lines spaced apart from each other in a first horizontal direction and each extending in a second horizontal direction orthogonal to the first horizontal direction, and disposed at the same level, wherein the plurality of erase control lines are grouped into a plurality of groups including a first group comprising erase control lines relatively close to a word line cut area and a second group comprising erase control lines relatively far from the word line cut area; A pass transistor circuit comprising a first pass transistor connected to the first group and a second pass transistor connected to the second group; and A non-volatile memory device comprising a memory cell array including a plurality of blocks, wherein each block is connected to the plurality of word lines and the plurality of erase control lines and includes a plurality of channel structures each extended in the vertical direction.
2. In paragraph 1, It further includes a plurality of string selection lines spaced apart from each other in the first horizontal direction and each extended in the second horizontal direction above the plurality of word lines, A non-volatile memory device characterized in that the plurality of erase control lines are each disposed above the plurality of string selection lines.
3. In paragraph 1, It further includes a plurality of ground selection lines spaced apart from each other in the first horizontal direction and each extended in the second horizontal direction at the lower part of the plurality of word lines, and A non-volatile memory device characterized in that the plurality of erase control lines are each disposed below the plurality of ground selection lines.
4. In paragraph 1, The above plurality of erase control lines include a plurality of GIDL (Gate Induced Drain Leakage) gate lines, and A non-volatile memory device characterized in that each of the plurality of vertical channel structures includes a GIDL select transistor connected to a corresponding GIDL gate line among the plurality of GIDL gate lines.
5. In paragraph 1, A non-volatile memory device characterized in that, during an erase operation for a selected block among the plurality of blocks, the voltage level of a first erase control voltage applied to the first group and the voltage level of a second erase control voltage applied to the second group are different from each other.
6. In paragraph 1, A non-volatile memory device characterized in that, during an erase operation for a selected block among the plurality of blocks, the time at which the first erase control voltage is applied to the first group and the time at which the second erase control voltage is applied to the second group are different.
7. In paragraph 1, A non-volatile memory device characterized in that, during an erase operation for a selected block among the plurality of blocks, the time at which the application of a first erase control voltage to the first group ends and the time at which the application of a second erase control voltage to the second group ends are different from each other.
8. In paragraph 1, The compensation value for the voltage level of the first erase control voltage for the first group according to the temperature of the non-volatile memory device is different from the compensation value for the voltage level of the second erase control voltage for the second group according to the temperature, or A non-volatile memory device characterized in that the compensation value for the application time of the first erase control voltage according to the above temperature is different from the compensation value for the application time of the second erase control voltage according to the above temperature.
9. In paragraph 1, the plurality of erase control lines are, A first erase control line, a second erase control line, and a third erase control line arranged along the first horizontal direction between the first word line cut area and the second word line cut area; and It includes a fourth erase control line, a fifth erase control line, and a sixth erase control line arranged along the first horizontal direction between the second word line cut area and the third word line cut area, and The above first, third, fourth, and sixth erase control lines are included in the first group, and A non-volatile memory device characterized in that the second and fifth erase control lines are included in the second group.
10. In Paragraph 9, The first pass transistor is commonly connected to the first, third, fourth, and sixth erase control lines, and transmits a first erase control voltage to the first, third, fourth, and sixth erase control lines during an erase operation for a selected block among the plurality of blocks. The second pass transistor is commonly connected to the second and fifth erase control lines, and transmits a second erase control voltage to the second and fifth erase control lines during the erase operation for the selection block. A non-volatile memory device characterized in that at least one of the voltage level and application time of the first erase control voltage is different from at least one of the voltage level and application time of the second erase control voltage.
11. In paragraph 1, the plurality of erase control lines are, A first erase control line, a second erase control line, a third erase control line, and a fourth erase control line arranged along the first horizontal direction between the first word line cut area and the second word line cut area; and It includes a fifth erase control line, a sixth erase control line, a seventh erase control line, and an eighth erase control line arranged along the first horizontal direction between the second word line cut area and the third word line cut area, and The above first, fourth, fifth, and eighth erasure control lines are included in the first group, and A non-volatile memory device characterized in that the second, third, sixth, and seventh erase control lines are included in the second group.
12. In Paragraph 11, The first pass transistor is commonly connected to the first, fourth, fifth, and eighth erase control lines, and transmits a first erase control voltage to the first, fourth, fifth, and eighth erase control lines during an erase operation for a selected block among the plurality of blocks. The second pass transistor is commonly connected to the second, third, sixth, and seventh erase control lines, and transmits a second erase control voltage to the second, third, sixth, and seventh erase control lines during the erase operation for the selection block, and A non-volatile memory device characterized in that at least one of the voltage level and application time of the first erase control voltage is different from at least one of the voltage level and application time of the second erase control voltage.
13. In paragraph 1, The plurality of erase control lines are grouped into the first group, the second group, and a third group comprising erase control lines further from the word line cut area than the second group, and The above plurality of erase control lines are, A first erase control line, a second erase control line, a third erase control line, a fourth erase control line, and a fifth erase control line arranged along the first horizontal direction between the first word line cut area and the second word line cut area; and It includes a sixth erase control line, a seventh erase control line, an eighth erase control line, a ninth erase control line, and a tenth erase control line arranged along the first horizontal direction between the second word line cut area and the third word line cut area, The above first, fifth, sixth, and tenth erase control lines are included in the first group, and The above second, fourth, sixth, and seventh erase control lines are included in the second group, and A non-volatile memory device characterized in that the above third and eighth erase control lines are included in the above third group.
14. In Paragraph 13, The above pass transistor circuit further includes a third pass transistor, and The first pass transistor is commonly connected to the first, fifth, sixth, and tenth erase control lines, and transmits a first erase control voltage to the first, fifth, sixth, and tenth erase control lines during an erase operation for a selected block among the plurality of blocks. The second pass transistor is commonly connected to the second, fourth, sixth, and seventh erase control lines, and transmits a second erase control voltage to the second, fourth, sixth, and seventh erase control lines during the erase operation for the selection block, and The third pass transistor is commonly connected to the third and eighth erase control lines, and transmits a third erase control voltage to the third and eighth erase control lines during the erase operation for the selection block. A non-volatile memory device characterized in that at least one of the voltage levels and application times of the first erase control voltage, the second erase control voltage, and the third erase control voltage is different from each other.
15. In paragraph 1, The plurality of word lines, the plurality of erase control lines, and the memory cell array are disposed in a memory cell area, and The above memory cell array includes a first metal pad, and The above non-volatile memory device is, It includes a second metal pad, and further includes a peripheral circuit region vertically connected to the memory cell region through the first metal pad and the second metal pad. A non-volatile memory device characterized in that the first metal pad and the second metal pad are connected by a bonding method.
16. A memory cell array comprising a plurality of memory cells and a plurality of erase control transistors, wherein the plurality of erase control transistors are each connected to a plurality of erase control lines arranged at the same level, and the plurality of erase control lines are grouped into a plurality of groups including a first group comprising erase control lines relatively close to a word line cut area and a second group comprising erase control lines relatively far from the word line cut area; A pass transistor circuit comprising a first pass transistor connected to the first group and a second pass transistor connected to the second group; and A non-volatile memory device comprising a control logic circuit that controls at least one of the voltage levels and application times of a first erase control voltage applied to a first pass transistor and a second erase control voltage applied to a second pass transistor differently in response to an erase command.
17. In Paragraph 16, The above plurality of erase control lines include a plurality of GIDL (Gate Induced Drain Leakage) gate lines, and A non-volatile memory device characterized in that the plurality of erase control transistors include GIDL select transistors connected to the plurality of GIDL gate lines.
18. In Paragraph 16, A non-volatile memory device characterized in that the voltage level of the first erase control voltage and the voltage level of the second erase control voltage are different from each other.
19. In Paragraph 16, A non-volatile memory device characterized in that the time at which the first erasure control voltage is applied to the first group and the time at which the second erasure control voltage is applied to the second group are different.
20. In Paragraph 16, A non-volatile memory device characterized in that the time at which the application of the first erase control voltage to the first group ends and the time at which the application of the second erase control voltage to the second group ends are different from each other.

Description

Non-volatile Memory Device The technical concept of the present disclosure relates to a memory device, and more specifically, to a non-volatile memory device having a multi-hole structure. Memory devices are used to store data and are classified into volatile memory devices and non-volatile memory devices. In response to the demand for increased capacity and miniaturization of non-volatile memory devices, a 3D memory device has been developed that includes multiple channel holes, i.e., multiple channel structures, extending vertically on a substrate. To further improve the integration density of the 3D memory device, the number of channel holes, i.e., channel structures, included in each memory block can be further increased. In the case of a non-volatile memory device having such a multi-hole structure, performance differences may occur due to differences in the intrinsic characteristics of the channel holes, i.e., channel structures. FIG. 1 is a block diagram showing a memory system according to one embodiment of the present disclosure. FIG. 2 is a block diagram showing a memory device according to one embodiment of the present disclosure. FIGS. 3 to 5 are circuit diagrams each showing a memory block according to some embodiments of the present disclosure. FIGS. 6a and 6b are perspective views showing memory blocks according to some embodiments of the present disclosure, respectively. FIGS. 7 to 9 respectively show the connections of a memory block, a pass transistor circuit, and a row decoder according to some embodiments of the present disclosure. FIG. 10 is a plan view showing a memory device according to one embodiment of the present disclosure. FIG. 11 is a cross-sectional view along the line Y1-Y1' of FIG. 10 according to one embodiment of the present disclosure. FIGS. 12 and FIGS. 13 each show parts of a memory device according to some embodiments of the present disclosure. FIGS. 14 to 16 are timing diagrams each illustrating an erase operation of a memory device according to some embodiments of the present disclosure. FIG. 17 is a plan view showing a memory device according to one embodiment of the present disclosure. FIG. 18 shows a part of a memory device according to one embodiment of the present disclosure. FIG. 19 is a plan view showing a memory device according to one embodiment of the present disclosure. FIG. 20 shows a part of a memory device according to one embodiment of the present disclosure. FIG. 21 is a block diagram showing a memory system according to one embodiment of the present disclosure. FIG. 22 shows a memory device having a COP structure according to one embodiment of the present disclosure. FIG. 23 is a cross-sectional view showing a memory device having a B-VNAND structure according to one embodiment of the present disclosure. FIG. 24 is a block diagram showing an SSD system to which a memory device according to one embodiment of the present disclosure is applied. Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. FIG. 1 is a block diagram showing a memory system (10) according to one embodiment of the present disclosure. Referring to FIG. 1, the memory system (10) may include a memory device (100) and a memory controller (200), and the memory device (100) may include a memory cell array (110), a pass transistor circuit (120), and a control logic circuit (130). The memory device (100) may be a non-volatile memory device, and in this specification, "memory device" refers to a "non-volatile memory device." The memory controller (200) can control the memory device (100) to read data stored in the memory device (100) or to program data in the memory device (100) in response to a read/write request from the host (HOST). Specifically, the memory controller (200) can control the programming, reading, and erasing operations for the memory device (100) by providing an address (ADDR), a command (CMD), and a control signal (CTRL) to the memory device (100). Additionally, data to be programmed (DATA) and data to be read (DATA) can be transmitted and received between the memory controller (200) and the memory device (100). The memory cell array (110) may include a plurality of memory cells, for example, the plurality of memory cells may be flash memory cells. Hereinafter, embodiments of the present disclosure will be described in detail with the example of the case where the plurality of memory cells are NAND flash memory cells. However, the present invention is not limited thereto, and in some embodiments, the plurality of memory cells may be resistive memory cells such as ReRAM (resistive RAM), PRAM (phase change RAM), or MRAM (magnetic RAM). A memory cell array (110) may be connected to a pass transistor circuit (120) through a plurality of erase control lines (GIDL_SSa, GIDL_SSb) placed a