KR-102962961-B1 - Non-volatile Memory Device

Abstract

A non-volatile memory device comprises a plurality of cell strings, each cell string comprising a memory cell array including memory cells connected to word lines and a string selection transistor connected to a string selection line, a plurality of page buffers, each page buffer including a forcing latch that stores forcing information and a page buffer circuit connected to a selected cell string through a bit line, and a control logic circuit that controls at least two of a first voltage applied to a string selection line in a first period before a bit line forcing operation is performed, a second voltage applied to a string selection line in a second period when a bit line forcing operation is performed, and a third voltage applied to a string selection line in a third period after a bit line forcing operation is performed differently from each other during a program operation for a selected word line.

Inventors

• 최용혁
• 이요한
• 박상원
• 유재덕

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20211028

Claims (20)

1. A memory cell array comprising a plurality of cell strings each extended vertically on a substrate, wherein each cell string comprises a plurality of memory cells each connected to a plurality of word lines and a string selection transistor connected to a string selection line; A page buffer circuit comprising a plurality of page buffers connected to the memory cell array, wherein each page buffer comprises a forcing latch storing forcing information and is connected to a select cell string via a bit line; and A non-volatile memory device comprising a control logic circuit that controls at least two of differently: a first voltage applied to a string selection line in a first section before a bit line forcing operation is performed to transmit forcing information to a selection cell string through the bit line, a second voltage applied to the string selection line in a second section where the bit line forcing operation is performed, and a third voltage applied to the string selection line in a third section after the bit line forcing operation is performed.
2. In paragraph 1, the control logic circuit is, A non-volatile memory device characterized by controlling the first and second voltages such that the voltage level of the first voltage is higher than the voltage level of the second voltage.
3. In paragraph 1, the control logic circuit is, A non-volatile memory device characterized by controlling the second and third voltages such that the voltage level of the second voltage is higher than the voltage level of the third voltage.
4. In paragraph 1, The plurality of word lines include a first word line relatively close to the substrate and a second word line relatively far from the substrate, and A non-volatile memory device characterized in that the first voltage when the selected word line corresponds to the first word line and the first voltage when the selected word line corresponds to the second word line have different voltage levels.
5. In paragraph 4, A non-volatile memory device characterized in that the voltage level of the first voltage when the selected word line corresponds to the first word line is higher than the voltage level of the first voltage when the selected word line corresponds to the second word line.
6. In paragraph 4, A non-volatile memory device characterized in that the second voltage when the selected word line corresponds to the first word line and the second voltage when the selected word line corresponds to the second word line have different voltage levels.
7. In paragraph 4, A non-volatile memory device characterized in that the third voltage when the selected word line corresponds to the first word line and the third voltage when the selected word line corresponds to the second word line have different voltage levels.
8. In paragraph 1, Each of the above page buffers further includes a bit line shut-off transistor driven according to a bit line shut-off signal, and A non-volatile memory device characterized in that the bit line shut-off voltage corresponding to the bit line shut-off signal is the same as the bit line forcing voltage in the second section, and accordingly, in the second section, each page buffer is electrically connected to the bit line to transmit the forcing information to the select cell string.
9. In paragraph 8, A non-volatile memory device characterized by applying a program voltage to the selected word line in the first section, the second section, and the third section.
10. In paragraph 8, Each of the above page buffers further includes a sensing latch that stores bit line setup information, and A non-volatile memory device characterized in that the bit line shut-off voltage is the same as the bit line setup voltage in the bit line setup section prior to the first section, and accordingly, in the bit line setup section, each page buffer is electrically connected to the bit line to transmit the bit line setup information to the selected cell string.
11. In Paragraph 10, A non-volatile memory device characterized by applying a power voltage to the selected word line during the bit line setup section.
12. In Paragraph 10, A non-volatile memory device characterized in that the control logic circuit controls the fourth voltage applied to the string selection line in the bit line setup section differently from at least one of the first voltage, the second voltage, and the third voltage during the program operation.
13. In Clause 12, the above control logic circuit is, A non-volatile memory device characterized by controlling the first and fourth voltages such that the voltage level of the first voltage is higher than the voltage level of the fourth voltage.
14. In Paragraph 12, The plurality of word lines include a first word line relatively close to the substrate and a second word line relatively far from the substrate, and A non-volatile memory device characterized in that the fourth voltage when the selected word line corresponds to the first word line and the fourth voltage when the selected word line corresponds to the second word line have different voltage levels.
15. In paragraph 1, Each of the above cell strings comprises a plurality of memory stacks, including a first memory stack extended in the vertical direction on the substrate and a second memory stack extended in the vertical direction above the first memory stack. The plurality of word lines include a first word line connected to the first memory stack, a second word line connected to the first memory stack and positioned above the first word line, a third word line connected to the second memory stack and positioned above the second word line, and a fourth word line connected to the second memory stack and positioned above the third word line. A non-volatile memory device characterized in that the control logic circuit controls at least one of the first voltage, the second voltage, and the third voltage differently for the first to fourth word lines.
16. A plurality of word lines, including a first word line relatively close to a substrate and a second word line relatively far from the substrate; A memory cell array comprising a plurality of cell strings each extended vertically on the substrate, wherein each cell string comprises a plurality of memory cells each connected to the plurality of word lines; A page buffer circuit comprising a plurality of page buffers connected to the memory cell array, wherein each page buffer is connected to a select cell string via a bit line, and each page buffer includes a bit line shut-off transistor driven according to a bit line shut-off signal and a forging latch storing forging information; and It includes a control logic circuit that controls a delay period in which a bit line shut-off voltage corresponding to the bit line shut-off signal maintains a ground voltage before a bit line forcing operation is performed to transmit the forcing information to the selected cell string through the bit line during a program operation for the selected word line, A non-volatile memory device characterized in that the length of the delay interval when the selected word line corresponds to the first word line is longer than the length of the delay interval when the selected word line corresponds to the second word line.
17. In Clause 16, the above control logic circuit is, A non-volatile memory device characterized by further controlling a step waveform in which the bit line shut-off voltage rises from the ground voltage to the bit line forcing voltage during the operation of the above program.
18. In Paragraph 17, The above step waveform includes a plurality of steps, and A non-volatile memory device characterized in that the above control logic circuit controls at least one of a cycle corresponding to a maintenance period of each of the plurality of steps and a step corresponding to a voltage difference between the plurality of steps.
19. In Paragraph 18, A non-volatile memory device characterized in that the length of the cycle when the selected word line corresponds to the first word line is different from the length of the cycle when the selected word line corresponds to the second word line.
20. In Paragraph 18, A non-volatile memory device characterized in that the size of the step when the selected word line corresponds to the first word line is different from the size of the step when the selected word line corresponds to the second word line.

Description

Non-volatile Memory Device The technical concept of the present disclosure relates to a memory device, and more specifically, to a non-volatile memory device having a cell string corresponding to a vertical channel structure. Memory devices are used to store data and are classified into volatile memory devices and non-volatile memory devices. In response to the demand for increased capacity and miniaturization of non-volatile memory devices, a 3D memory device has been developed that includes multiple vertical channel structures extending vertically on a substrate. To further improve the integration density of the 3D memory device, the length of each vertical channel structure may increase as the number of multiple word lines stacked vertically on the upper surface of the substrate increases. Due to this increase in the length of the vertical channel structures, a channel recovery degradation phenomenon may occur in which the bit line voltage is not properly transmitted across the entire channel region. FIG. 1 is a block diagram showing a memory system according to one embodiment of the present disclosure. FIG. 2 is a block diagram showing a memory device according to one embodiment of the present disclosure. FIGS. 3 to 5 are circuit diagrams each showing a memory block according to some embodiments of the present disclosure. FIGS. 6a and 6b are perspective views showing memory blocks according to some embodiments of the present disclosure, respectively. FIG. 7 shows the connection relationship between a memory cell array and a page buffer circuit according to one embodiment of the present disclosure. FIG. 8 shows a page buffer according to one embodiment of the present disclosure. FIG. 9 is a graph showing the threshold voltage dispersion of memory cells according to an exemplary embodiment of the present disclosure. FIG. 10 is a timing diagram showing the program operation of a memory device according to one embodiment of the present disclosure. FIG. 11a schematically illustrates a memory device according to one embodiment of the present disclosure, and FIG. 11b is a table showing the voltage applied to the string selection line according to the selected word line during the program operation of the memory device of FIG. 11a according to one embodiment of the present disclosure. FIG. 12a schematically illustrates a memory device according to one embodiment of the present disclosure, and FIG. 12b is a table showing the voltage applied to the string selection line according to the selected word line during the program operation of the memory device of FIG. 12a according to one embodiment of the present disclosure. FIG. 13a is a timing diagram showing the voltage applied to the string selection line during a program operation for a first group according to one embodiment of the present disclosure, and FIG. 13b is a timing diagram showing the voltage applied to the string selection line during a program operation for a second group according to one embodiment of the present disclosure. FIG. 14 is a timing diagram showing a program operation for a memory device according to one embodiment of the present disclosure. FIG. 15a shows the voltage waveform of a bit line shut-off signal during a program operation for a memory device according to one embodiment of the present disclosure, and FIG. 15b shows the control operation of a bit line selection signal according to a selected word line during a program operation according to one embodiment of the present disclosure. FIG. 16 shows a memory device having a COP structure according to one embodiment of the present disclosure. FIG. 17 is a cross-sectional view showing a memory device having a B-VNAND structure according to one embodiment of the present disclosure. FIG. 18 is a block diagram showing an SSD system to which a memory device according to one embodiment of the present disclosure is applied. Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. FIG. 1 is a block diagram showing a memory system (10) according to one embodiment of the present disclosure. Referring to FIG. 1, the memory system (10) may include a memory device (100) and a memory controller (200), and the memory device (100) may include a memory cell array (110), a control logic circuit (120), and a page buffer circuit (130). The memory device (100) may be a non-volatile memory device, and in this specification, "memory device" refers to a "non-volatile memory device." The memory controller (200) can control the memory device (100) to read data stored in the memory device (100) or to program data in the memory device (100) in response to a read/write request from the host (HOST). Specifically, the memory controller (200) can control the programming, reading, and erasing operations for the memory device (1