KR-102962962-B1 - INTEGRATED CIRCUIT DEVICES INCLUDING TRANSISTOR STACKS HAVING DIFFERENT THRESHOLD VOLTAGES AND METHODS OF FORMING THE SAME

KR102962962B1KR 102962962 B1KR102962962 B1KR 102962962B1KR-102962962-B1

Abstract

An integrated circuit device may include two transistor stacks comprising lower transistors having different threshold voltages and upper transistors having different threshold voltages. The gate insulators of the lower transistors may have different dipole elements or different area densities, and the upper transistors may have different gate electrode structures.

Inventors

임정혁
서강일
손길환
김기일

Assignees

삼성전자주식회사

Dates

Publication Date: 20260508
Application Date: 20220214
Priority Date: 20210728

Claims (20)

It includes a first CFET (complementary field effect transistor) stack and a second CFET stack on a substrate, The above first CFET stack is: A first upper transistor comprising a first upper active region and a first upper gate work function layer having a first thickness on the first upper active region; and A first lower transistor comprising a first lower active region, a first lower gate insulator comprising a first dipole element of a first area density, and a first lower gate work function layer on the first lower gate insulator, and The above second CFET stack is: A second upper transistor comprising a second upper active region and a second upper gate work function layer having a second thickness on the second upper active region; and A second lower transistor comprising a second lower active region, a second lower gate insulator comprising a second dipole element having a second area density, and a second lower gate work function layer on the second lower gate insulator, and When the first dipole element and the second dipole element have different conductivity types, or when the first dipole element and the second dipole element have the same conductivity type, the first area density is different from the second area density, and The above first thickness is an integrated circuit element different from the above second thickness.
In paragraph 1, An integrated circuit device in which the first lower gate work function layer and the second lower gate work function layer have the same thickness and include the same material.
In paragraph 2, The first lower transistor further includes a first lower gate metal layer on the first lower gate work function layer, and the second lower transistor further includes a second lower gate metal layer on the second lower gate work function layer. An integrated circuit device comprising the first lower gate metal layer and the second lower gate metal layer, wherein the first lower gate metal layer and the second lower gate metal layer comprise the same material.
In paragraph 2, The first lower transistor and the second lower transistor are integrated circuit devices having different threshold voltages.
In paragraph 1, The first dipole element and the second dipole element have different conductivity types, An integrated circuit element in which the first dipole element is lanthanum (La), yttrium (Y), strontium (Sr), lutetium (Lu), barium (Ba), or magnesium (Mg), and the second dipole element is aluminum (Al), hafnium (Hf), titanium (Ti), zirconium (Zr), tantalum (Ta), or scandium (Sc).
In paragraph 1, The first dipole element and the second dipole element have the same conductivity type, and An integrated circuit element in which the first dipole element and the second dipole element are each independently lanthanum (La), yttrium (Y), strontium (Sr), lutetium (Lu), barium (Ba), or magnesium (Mg), or each independently aluminum (Al), hafnium (Hf), titanium (Ti), zirconium (Zr), tantalum (Ta), or scandium (Sc).
In paragraph 1, A first etching prevention layer extending between the first upper gate work function layer and the first lower gate work function layer; and It further includes a second etching prevention layer extending between the second upper gate work function layer and the second lower gate work function layer, and An integrated circuit device comprising the first etching prevention layer and the second etching prevention layer having the same thickness and containing the same material.
In Paragraph 7, The first etching prevention layer and the second etching prevention layer comprise ruthenium (Ru), platinum (Pt), palladium (Pd), or tantalum nitride (TaN) in an integrated circuit device.
In Paragraph 7, The first etch prevention layer comprises a first portion extending on the upper surface of the first lower transistor and a second portion extending between the first upper active region and the first upper gate work function layer, The second etch prevention layer comprises a first portion extending on the upper surface of the second lower transistor and a second portion extending between the second upper active region and the second upper gate work function layer, forming an integrated circuit device.
In paragraph 1, It further includes a third CFET stack on the above substrate, The above third CFET stack is: A third upper transistor comprising a third upper active region and a third upper gate work function layer having a third thickness on the third upper active region, wherein the third thickness is different from the first and second thicknesses; and An integrated circuit device comprising a third lower active region, a third lower gate insulator without dipole elements, and a third lower gate work function layer on the third lower gate insulator, and a third lower transistor.
In Paragraph 10, An integrated circuit device in which the first, second, and third lower gate work function layers have the same thickness and contain the same material.
A step of forming a first pre-CFET (complementary field effect transistor) stack and a second pre-CFET stack on an insulating layer on a substrate, wherein the first pre-CFET stack is located at a first opening of the insulating layer and includes a first upper active region, a first upper gate insulator, a first lower active region, and a first lower gate insulator including a first dipole element, and the second pre-CFET stack is located at a second opening of the insulating layer and includes a second upper active region, a second upper gate insulator, a second lower active region, and a second lower gate insulator including a second dipole element; A step of forming a preliminary lower gate work function layer on the first and second preliminary CFET stacks; A step of forming a preliminary lower gate metal layer on the above preliminary lower gate work function layer; A step of removing the preliminary lower gate work function layer and the preliminary lower gate metal layer from the upper portions of the first and second openings to form a first lower gate work function layer and a first lower gate metal layer on the first lower gate insulator, and forming a second lower gate work function layer and a second lower gate metal layer on the second lower gate insulator; A method for manufacturing an integrated circuit device comprising the step of forming a first upper gate work function layer and a first upper gate metal layer on the first upper gate insulator above the first opening, and forming a second upper gate work function layer and a second upper gate metal layer on the second lower gate insulator above the second opening.
In Paragraph 12, The step of forming the first preliminary CFET stack and the second preliminary CFET stack is: A step of forming a first structure and a second structure in the first opening and the second opening of the insulating layer, respectively, wherein the first structure comprises the first upper active region, the first upper gate insulator, the first lower active region, and the first preliminary lower gate insulator, and the second structure comprises the second upper active region, the second upper gate insulator, the second lower active region, and the second preliminary lower gate insulator; A step of contacting the first preliminary lower gate insulator and forming a first dipole layer comprising a first dipole element; A step of performing a first annealing process to form the first lower gate insulator by diffusing the first dipole element into the first pre-lower gate insulator; A step of contacting the second pre-lower gate insulator and forming a second dipole layer containing a second dipole element after the first annealing process; and A method for manufacturing an integrated circuit device comprising the step of performing a second annealing process to form the second lower gate insulator by diffusing the second dipole element into the second preliminary lower gate insulator.
In Paragraph 13, The first dipole element and the second dipole element have the same conductivity type, and A method for manufacturing an integrated circuit device in which the first annealing process is performed at a first temperature different from the second temperature at which the second annealing process is performed.
In Paragraph 13, The first dipole element and the second dipole element have the same conductivity type, and A method for manufacturing an integrated circuit element in which the first dipole layer has a first thickness different from the second thickness of the second dipole layer.
In Paragraph 13, A method for manufacturing an integrated circuit element in which the first dipole element and the second dipole element have different conductivity types.
In Paragraph 13, A method for manufacturing an integrated circuit element in which the first dipole element and the second dipole element are each independently lanthanum (La), yttrium (Y), strontium (Sr), lutetium (Lu), barium (Ba), or magnesium (Mg), or each independently aluminum (Al), hafnium (Hf), titanium (Ti), zirconium (Zr), tantalum (Ta), or scandium (Sc).
In Paragraph 12, The method further includes the step of performing a selective atomic layer deposition process before forming the first upper gate work function layer and the first upper gate metal layer and before forming the second upper gate work function layer and the second upper gate metal layer to form a first etch prevention layer on the first lower gate work function layer and the first lower gate metal layer, and forming a second etch prevention layer on the second lower gate work function layer and the second lower gate metal layer. The first etching prevention layer exposes a first portion of the insulating layer defining the upper portion of the first opening, and the second etching prevention layer exposes a second portion of the insulating layer defining the upper portion of the second opening. A method for manufacturing an integrated circuit device in which the first upper gate work function layer and the first upper gate metal layer are formed on the first etching prevention layer, and the second upper gate work function layer and the second upper gate metal layer are formed on the second etching prevention layer.
In Paragraph 12, The method further includes the step of conformally depositing an etch-preventing layer on the upper portions of the first and second openings after forming the first lower gate work function layer and the first lower gate metal layer and after forming the second lower gate work function layer and the second lower gate metal layer. A method for manufacturing an integrated circuit device, wherein the etching prevention layer comprises a first portion extending on the upper surface of the first lower gate work function layer and the first lower gate metal layer, a second portion extending between the first upper gate insulator and the first upper gate work function layer, a third portion extending on the upper surface of the second lower gate work function layer and the second lower gate metal layer, and a fourth portion extending between the second upper gate insulator and the second upper gate work function layer.
In Paragraph 12, A method for manufacturing an integrated circuit device in which the first upper gate work function layer and the second upper gate work function layer have different thicknesses.

Description

Integrated circuit devices including transistor stacks having different threshold voltages and methods of forming the same The present invention relates generally to the field of electronics, and in particular to an integrated circuit element including a stacked transistor. Integrated circuit devices containing stacked transistors, such as complementary field effect transistor (CFET) stacks, have been introduced to reduce their area to nearly half that of their non-stacked devices. While it is advantageous to include multiple stacked transistors with different threshold voltages in the device to reduce leakage power, it can be difficult to form a lower transistor with a different threshold voltage using conventional methods because the upper transistor overlaps with the lower transistor. An example of the prior art is disclosed in US 10,825,736 B1. FIG. 1 shows a cross-sectional view of a CFET stack of an integrated circuit device according to some embodiment of the present invention. FIGS. 2a and 2b are tables showing the conductivity type and area density of dipole elements of a gate insulator according to some embodiments of the present invention. FIG. 3 shows a cross-sectional view of a CFET stack of an integrated circuit device according to some embodiments of the present invention. FIG. 4 illustrates a cross-sectional view of a CFET stack of an integrated circuit device according to some embodiments of the present invention. FIGS. 5 to 11 are cross-sectional views illustrating a method for forming an integrated circuit element according to some embodiments of the present invention. FIGS. 12 to 14 are cross-sectional views illustrating a method for forming an integrated circuit element according to some embodiments of the present invention. FIG. 15 is a flowchart of a method for forming an integrated circuit element according to some embodiments of the present invention. A method for forming an integrated circuit device including a CFET stack may include the step of forming a lower gate electrode of a lower transistor at the bottom of a deep aperture (i.e., an aperture having a high aspect ratio). Accordingly, it may be difficult to form lower transistors having different threshold voltages by forming different lower gate work function layers, because forming such lower gate work function layers may require multiple patterning processes. According to some embodiments of the present invention, lower transistors having different threshold voltages may be formed by forming different dipole elements or gate insulators having different dipole area densities, and the lower gate work function layers of the lower transistors may have the same thickness and may contain the same material(s). Therefore, lower transistors having different threshold voltages may be formed without multiple patterning processes. Additionally, the height of the lower transistor may be uniform as the lower transistor is formed by removing a lower gate work function layer containing the same thickness and the same material. According to some embodiments of the present invention, an upper transistor having a different threshold voltage can be formed by forming an upper gate work function layer having a different thickness and/or different material. Accordingly, an annealing process for dipole diffusion performed at a high temperature can be omitted, and the already formed lower transistor can be not damaged during such a high-temperature process. FIG. 1 illustrates a cross-sectional view of a CFET stack of an integrated circuit element (1000) according to some embodiment of the present invention. The cross-sectional view is taken along the channel width direction of the transistors of the CFET stack. The integrated circuit element (1000) may be a monolithic CFET device in which transistors are stacked on a single substrate (e.g., substrate (100)). Referring to FIG. 1, the integrated circuit element (1000) may include a first CFET stack (CFET1), a second CFET stack (CFET2), and a third CFET stack (CFET3) on the substrate (100). A first insulating layer (42) may be optionally provided between the substrate (100) and the first, second, and third CFET stacks (CFET1, CFET2, CFET3) to reduce substrate leakage current. In some embodiments, the first insulating layer (42) may be omitted, and the first, second, and third CFET stacks (CFET1, CFET2, CFET3) may be provided directly on the substrate (100). For example, the first insulating layer (42) may comprise silicon oxide and/or a material having a dielectric constant lower than that of silicon oxide or silicon nitride. A second insulating layer (46) provided on the substrate (100) may be provided on each of the first, second, and third CFET stacks (CFET1, CFET2, CFET3). For example, the second insulating layer (46) may cover the sides of the first, second, and third CFET stacks (CFET1, CFET2, CFET3). The substrate (100) may include an upper surface (100U) facing the first, second, and third CFE