KR-102962965-B1 - CHIP PACKAGE STRUCTURE WITH CONDUCTIVE ADHESIVE LAYER AND METHOD FOR FORMING THE SAME

KR102962965B1KR 102962965 B1KR102962965 B1KR 102962965B1KR-102962965-B1

Abstract

A method for forming a chip package structure is provided. The method comprises the step of providing a wiring board comprising a substrate, a pad, and a polymer layer. The polymer layer is positioned over the substrate and the pad, and the polymer layer has a first opening that exposes the pad. The method comprises the step of forming a conductive adhesive layer over the polymer layer and the pad. The conductive adhesive layer is in direct contact with the polymer layer and the pad and conformally covers them. The method comprises the step of forming a nickel layer over the conductive adhesive layer. The nickel layer is thicker than the conductive adhesive layer, and the nickel layer and the conductive adhesive layer are made of different materials. The method comprises the step of bonding a chip to the wiring board through a conductive bump. The conductive bump is located between the nickel layer and the chip.

Inventors

슈 쿠오-칭
첸 유-후안
첸 첸-시엔

Assignees

타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드

Dates

Publication Date: 20260511
Application Date: 20240524
Priority Date: 20200401

Claims (9)

As a method for forming a chip package structure, A step of providing a wiring board including a substrate and pads; A step of forming a conductive adhesive layer on the above pad; Step of forming a nickel layer on the conductive adhesive layer above - the nickel layer has a first lower surface and a bottom surface, the first lower surface is higher than the bottom surface, and the conductive adhesive layer has a second lower surface, the first lower surface is at the same height as the second lower surface -; A step of forming a palladium layer on a nickel layer such that the palladium layer covers the uppermost surface and sidewall surface of the nickel layer; A step of forming the gold layer on the palladium layer such that the gold layer covers the uppermost surface and the sidewall surface of the palladium layer; and A step of bonding the chip to the wiring substrate through a conductive bump - the conductive bump is located between the nickel layer and the chip - A method for forming a chip package structure including
In paragraph 1, A method for forming a chip package structure, wherein the palladium layer and the gold layer are dissolved in the conductive bump after the chip is bonded to the wiring substrate, and the upper portion of the nickel layer extends into the conductive bump.
In paragraph 2, The step of forming the conductive adhesive layer, the nickel layer, the palladium layer, and the gold layer is: A step of forming a layer of conductive adhesive material on the above pad; Step of forming a mask layer on the conductive adhesive material layer - the mask layer has an opening that exposes the conductive adhesive material layer on or adjacent to the pad -; A step of forming the nickel layer within the opening; A step of forming the palladium layer on the nickel layer; A step of forming the gold layer on the palladium layer; and A method for forming a chip package structure comprising the step of removing the mask layer and the conductive adhesive material layer below the mask layer—the conductive adhesive material layer remaining below the nickel layer forms the conductive adhesive layer.
In paragraph 2, The step of forming the conductive adhesive layer above is: A step of forming a layer of conductive adhesive material on the above pad; A step of forming a mask layer on the conductive adhesive material layer on or adjacent to the pad; Step of removing the conductive adhesive material layer exposed by the mask layer - the conductive adhesive material layer remaining under the mask layer forms the conductive adhesive layer -; and A method for forming a chip package structure comprising the step of removing the above mask layer.
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In paragraph 2, Step of forming a solder ball on a nickel layer after forming the gold layer on the palladium layer - the gold layer and the palladium layer are dissolved in the solder ball, and a portion of the conductive bump is formed from the solder ball - A method for forming a chip package structure, further comprising
As a method for forming a chip package structure, A step of providing a wiring board comprising a substrate and a first pad - the first pad is on a first surface of the substrate -; A step of forming a first conductive adhesive layer on the first pad; A step of forming a solder structure on the first conductive adhesive layer, wherein the step of forming the solder structure is A step of forming a nickel layer on the first conductive adhesive layer - the nickel layer is on the first conductive adhesive layer, the nickel layer has a first lower surface and a bottom surface, the first lower surface is higher than the bottom surface, the first conductive adhesive layer has a second lower surface, and the first lower surface is at the same height as the second lower surface - ; A step of forming the palladium layer on the nickel layer such that the palladium layer covers the uppermost surface and the sidewall surface of the nickel layer; and A step of forming the solder structure, comprising the step of forming the gold layer on the palladium layer such that the gold layer covers the uppermost surface and the sidewall surface of the palladium layer; and A step of bonding a chip to a wiring substrate through an under bump metallurgy layer and a first conductive bump - the under bump metallurgy layer is located between the chip and the first conductive bump - A method for forming a chip package structure including
As a chip package structure, A wiring board comprising a substrate, a first pad, and a second pad—the first pad and the second pad are each on a first surface and a second surface of the substrate, respectively, and the first pad is narrower than the second pad—; A nickel layer on the first pad above - the nickel layer has a T-shape in the cross-sectional view of the nickel layer -; Chip on the wiring board above; A conductive bump between the nickel layer and the chip; and A conductive adhesive layer on the first pad above - the nickel layer is on the conductive adhesive layer, the nickel layer has a first lower surface and a bottom surface, the first lower surface is higher than the bottom surface, and the conductive adhesive layer has a second lower surface, the first lower surface is at the same height as the second lower surface - A chip package structure comprising, wherein the conductive bump comprises palladium and gold dispersed therein and covers the uppermost surface and sidewalls of the nickel layer.
In paragraph 8, A chip package structure in which the nickel layer covers the sidewalls and the top surface of the conductive adhesive layer.

Description

Chip package structure having a conductive adhesive layer and method for forming the same Semiconductor devices are used in various electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and by patterning various material layers using lithography to form circuit components and elements. Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. Individual dies are singulated by sawing the integrated circuits along a scribe line. The individual dies are then packaged individually. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as feature sizes continue to decrease, the manufacturing process becomes increasingly difficult to perform. Consequently, forming reliable packages with electronic components having high integration density is a challenging task. The aspects of the present disclosure are best understood from the following detailed description when read with reference to the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to a constant scale. In practice, the dimensions of various features may be increased or decreased at will for the sake of clarity of discussion. FIGS. 1a to 1e are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments. FIG. 2 is a cross-sectional view of a stage of a process for forming a chip package structure according to some embodiments. FIGS. 3a to 3c are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments. FIG. 4 is a cross-sectional view of a stage of a process for forming a chip package structure according to some embodiments. FIGS. 5a to 5d are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments. FIGS. 6a to 6e are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments. FIGS. 7a to 7c are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments. FIGS. 8a to 8d are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments. FIGS. 9a to 9c are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments. FIGS. 10a to 10c are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments. FIGS. 11a to 11c are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments. The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. To simplify the disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Additionally, the disclosure may repeat reference numbers and/or letters in various examples. Such repetition is for simplicity and clarity and does not affect the relationships between the various embodiments and/or configurations discussed by themselves. Furthermore, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used to describe the relationship between one element or feature and another element(s) or feature(s) as illustrated in the drawings for ease of description in this specification. Spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and spatially relative descriptors used in this specification may likewise be interpreted accordingly. It should be understood that additional operations may be provided prior to, during, and after the method, and that some of the described operations may be replaced or removed