KR-102962967-B1 - SEMICONDUCTOR DEVICE AND METHOD

Abstract

An embodiment comprises a device, wherein the device comprises a first die comprising a first surface and a second surface opposite the first surface. The first die comprises a plurality of through-substrate vias (TSVs) exposed from the second surface of the first die. The device also comprises a guard ring surrounding the plurality of TSVs. The device also comprises a dummy metallization pattern surrounding the guard ring. The device also comprises an active metallization pattern connected to an active device within the first die.

Inventors

• 시 양-신
• 왕 콴-순
• 양 치 신

Assignees

• 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드

Dates

Publication Date

20260508

Application Date

20240820

Priority Date

20240103

Claims (10)

1. In terms of the device, A first die comprising a first surface and a second surface opposite the first surface, and The above first die is: A plurality of through substrate vias (TSVs) exposed from the second surface of the first die; A guard ring surrounding the plurality of TSVs; and Dummy metallized pattern surrounding the above guard ring Includes, The above dummy metallization pattern extends between the plurality of TSVs, and A device in which a gap at the intersection of the dummy metallization patterns between the plurality of TSVs separates the dummy metallization patterns.
2. A device according to claim 1, wherein the guard ring extends between the plurality of TSVs.
3. A device according to paragraph 2, wherein the guard ring surrounding the plurality of TSVs and extending between the plurality of TSVs is a continuous guard ring.
4. In paragraph 1, the first die is, An active metallization pattern connected to an active device within the first die; Substrate - the first surface is on the first side of the substrate -; A first interconnect structure on the first side of the substrate - the guard ring, the dummy metallization pattern, and the active metallization pattern are within the first interconnect structure -; and A second interconnect structure on the second side of the substrate - the metallization pattern of the second interconnect structure is electrically coupled to at least one of the plurality of TSVs - A device that further includes
5. In paragraph 4, the first die is, A device further comprising a high-kappa material on the first interconnect structure and the plurality of TSVs.
6. In paragraph 1, A device further comprising a second die bonded to the first surface of the first die, wherein the first surface comprises bond pads.
7. delete
8. A device according to claim 1, wherein the dummy metallization pattern extending between the plurality of TSVs is physically connected to the guard ring surrounding the plurality of TSVs.
9. In terms of method, A step of forming a first die comprising a first surface and a second surface opposite the first surface - the step of forming the first die is: A step of forming a first interconnect structure on a first substrate - the first interconnect structure includes an active metallization pattern, a guard ring, and a dummy metallization pattern -; A step of forming a through-substrate via (TSV) through the first interconnection structure and the first substrate - wherein the guard ring surrounds the TSV within the first interconnection structure, and the dummy metallization pattern surrounds the guard ring -; and Step of forming a bond pad on the first interconnection structure and connected to the TSV and the active metallization pattern of the first interconnection structure - the bond pad is on the first surface of the first die, and the TSV is exposed on the second surface of the first die - Includes -; A step of forming a second die comprising a first surface and a second surface opposite the first surface; and A step of bonding the first surface of the first die to the first surface of the second die. Includes, The above dummy metallization pattern extends between the TSVs, and A method in which a gap at the intersection of the dummy metallization patterns between the TSVs separates the dummy metallization patterns.
10. In terms of method, A step of forming a first die comprising a first surface and a second surface opposite the first surface The step of forming the first die, including: A step of forming a first interconnect structure on a first substrate - the first interconnect structure includes an active metallization pattern, a guard ring, and a dummy metallization pattern -; A step of forming a through-substrate via (TSV) through the first interconnection structure and the first substrate - the guard ring is a continuous structure that surrounds the TSV within the first interconnection structure and extends between the TSVs, and the dummy metallization pattern surrounds the guard ring -; Step of forming a second interconnect structure on the first substrate - the second interconnect structure is on the side of the first substrate opposite to the first interconnect structure - Includes, The above dummy metallization pattern extends between the TSVs, and A method in which a gap at the intersection of the dummy metallization patterns between the TSVs separates the dummy metallization patterns.

Description

Semiconductor Device and Method Priority Claims and Cross-References This application claims the benefit of U.S. Provisional Application No. 63/607,852 filed on December 8, 2023, under the title "SEMICONDUCTOR DEVICE AND METHOD" and U.S. Provisional Application No. 63/520,717 filed on August 21, 2023, under the title "TSV OPTIMIZED CLUSTER FOR HIGH PPAC", by which said applications are incorporated herein by reference. The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, improvements in integration density have resulted from the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for miniaturizing electronic devices has grown, the need for smaller and more creative packaging technologies for semiconductor dies has emerged. An example of such a packaging system is Package-on-Package (PoP) technology. In PoP devices, an upper semiconductor package is stacked on top of a lower semiconductor package to provide a high level of integration and component density. PoP technology generally enables the production of semiconductor devices with enhanced functionality and small footprints on printed circuit boards (PCBs). The embodiments of the present disclosure are best understood from the following detailed description when read together with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In practice, the dimensions of various features may be increased or decreased at will for the sake of clarity of discussion. FIGS. 1a, FIGS. 1b, FIGS. 2, FIGS. 3, FIGS. 4, FIGS. 5, FIGS. 6a, FIGS. 6b, FIGS. 6c, FIGS. 7, FIGS. 8 and FIGS. 9 illustrate cross-sectional and plan views of intermediate stages in the formation of a die according to embodiments. FIGS. 10 to 14 illustrate cross-sectional views of intermediate stages in the formation of a package according to embodiments. FIGS. 15a, FIGS. 15b, FIGS. 15c, and FIGS. 15d illustrate cross-sectional and plan views of an intermediate stage in the formation of a die according to embodiments. FIG. 16 illustrates a cross-sectional view of a package according to embodiments. FIG. 17 illustrates a cross-sectional view of a package according to embodiments. The following disclosure provides many different embodiments or examples for implementing different features of the present invention. For the sake of simplicity, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, etc. are considered. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Additionally, the present disclosure may repeat reference numbers and/or letters in various examples. Such repetition is for simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and/or configurations discussed. Additionally, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein for convenience of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the drawings. Spatially relative terms are intended to include other directions of the device in use or operation in addition to the directions illustrated in the drawings. The device may be oriented differently (rotated 90 degrees or rotated in other directions), and the spatially relative terms used herein may be interpreted similarly accordingly. The embodiments discussed herein may be discussed for specific situations, namely TSV (through substrate via) clusters with reduced pitch between adjacent TSVs. In some embodiments, the TSV cluster has a guard ring wall merged between adjacent TSVs. In some embodiments, a dummy interconnect structure is located between adjacent TSVs of the TSV cluster instead of the merged guard ring wall. By having a guard ring wall merged or a dummy interconnect structure between adjacent TSVs of the TSV cluster, the pitch between adjacent TSVs can be reduced. Thus, the total area consumed by the TSV cluster is reduced, and more area can be used for other functions of the device, or the device size can be reduced. In some embodiments, the disclosed TSV cluster may be applied to a device (e.g., a chip or die) or a package (e.g., a system on integrated chip (SoIC), a chip-on-wafer (CoW) package structure, or a wafer-on-wafer (WoW) package stru