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KR-102963037-B1 - Semiconductor device

KR102963037B1KR 102963037 B1KR102963037 B1KR 102963037B1KR-102963037-B1

Abstract

The present invention provides a semiconductor device capable of improving device performance and reliability. The semiconductor device comprises an active pattern including a lower pattern extending in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction, a gate structure disposed on the lower pattern and including a gate electrode, a gate insulating film, and a gate spacer, and a source/drain pattern disposed on the lower pattern and connected to each sheet pattern, wherein the sheet pattern includes a first sheet pattern and a second sheet pattern closest to each other in a second direction, and the second sheet pattern is disposed between the first sheet pattern and the lower pattern, and each first sheet pattern and the second sheet pattern includes an upper surface and a lower surface opposite in the second direction, and the lower surface of the first sheet pattern faces the upper surface of the second sheet pattern, and the first upper width of the upper surface of the first sheet pattern in the first direction is greater than the first lower width of the lower surface of the first sheet pattern in the first direction, and the second upper width of the upper surface of the second sheet pattern in the first direction is smaller than the second lower width of the lower surface of the second sheet pattern in the first direction.

Inventors

  • 김겸
  • 김다혜
  • 김영광
  • 김진범
  • 전경빈

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260508
Application Date
20221103

Claims (10)

  1. An active pattern comprising a lower pattern extended in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction; A gate structure disposed on the lower pattern above and comprising a gate electrode, a gate insulating film, and a gate spacer; and It includes a source/drain pattern disposed on the lower pattern and connected to each of the sheet patterns, The above sheet pattern includes the first sheet pattern and the second sheet pattern closest to each other in the second direction, and The second sheet pattern is positioned between the first sheet pattern and the lower pattern, and Each of the above-mentioned first sheet pattern and the above-mentioned second sheet pattern includes an upper surface and a lower surface opposite in the above-mentioned second direction, and The lower surface of the first sheet pattern faces the upper surface of the second sheet pattern, The first upper width in the first direction of the upper surface of the first sheet pattern is larger than the first lower width in the first direction of the lower surface of the first sheet pattern, A semiconductor device in which the second upper width in the first direction of the upper surface of the second sheet pattern is smaller than the second lower width in the first direction of the lower surface of the second sheet pattern.
  2. In Article 1, The first sheet pattern is a semiconductor device located at the top of a plurality of sheet patterns.
  3. In Article 2, A semiconductor device in which the difference between the first upper width and the first lower width is greater than the difference between the second lower width and the second upper width.
  4. In Article 1, A semiconductor device in which the point where the width of the source/drain pattern in the first direction is maximum is located between the lower surface of the first sheet pattern and the upper surface of the second sheet pattern.
  5. In Article 1, The above sheet pattern further includes a third sheet pattern disposed on the first sheet pattern, and The above third sheet pattern is located at the top of the plurality of above sheet patterns, and The lower surface of the above third sheet pattern faces the above lower pattern, A semiconductor device in which the width of the upper surface of the third sheet pattern in the first direction is greater than the width of the lower surface of the third sheet pattern in the first direction.
  6. In Article 1, The above sheet pattern further includes a third sheet pattern disposed between the lower pattern and the second sheet pattern, and The lower surface of the above third sheet pattern faces the above lower pattern, A semiconductor device in which the width of the upper surface of the third sheet pattern in the first direction is smaller than the width of the lower surface of the third sheet pattern in the first direction.
  7. In Article 6, The third sheet pattern is closest to the second sheet pattern, and The gate structure comprises an inner gate structure disposed between the second sheet pattern and the third sheet pattern, and including the gate electrode and the gate insulating film. The inner gate structure includes an upper surface in contact with the lower surface of the second sheet pattern and a lower surface in contact with the upper surface of the third sheet pattern. At the center of the thickness of the inner gate structure, the inner gate structure has a center width in a first direction, The center width of the inner gate structure is smaller than the width in the first direction of the upper surface of the inner gate structure, and A semiconductor device in which the center width of the inner gate structure is smaller than the width in the first direction of the lower surface of the inner gate structure.
  8. In Article 1, The gate structure comprises an inner gate structure disposed between the first sheet pattern and the second sheet pattern, and including the gate electrode and the gate insulating film. The above source/drain pattern is a semiconductor device in contact with the gate insulating film of the above inner gate structure.
  9. An active pattern comprising a lower pattern extended in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction; A gate structure disposed on the lower pattern above and comprising a gate electrode, a gate insulating film, and a gate spacer; and It includes a source/drain pattern disposed on the lower pattern and connected to each of the sheet patterns, The above source/drain pattern includes a lower source/drain region in contact with the lower pattern and an upper source/drain region disposed on the lower source/drain region. The gate structure comprises an inner gate structure disposed between the lower pattern and the sheet pattern and between adjacent sheet patterns, and including the gate electrode and the gate insulating film. The above source/drain pattern contacts the gate insulating film of the inner gate structure, and The upper source/drain region includes an upper source/drain outer surface in contact with the sheet pattern and the inner gate structure, and The lower source/drain region is in contact with the sheet pattern and the inner gate structure, and includes a lower source/drain outer surface directly connected to the upper source/drain outer surface, and The sign of the slope of the upper source/drain outer surface is opposite to the sign of the slope of the lower source/drain outer surface, and The intersection point where the upper source/drain outer surface and the lower source/drain outer surface meet is a semiconductor device in contact with the inner gate structure.
  10. An active pattern comprising a lower pattern extended in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction; A gate structure disposed on the lower pattern above and comprising a gate electrode and a gate insulating film; and It includes a source/drain pattern disposed on the lower pattern and connected to each of the sheet patterns, The gate structure comprises an inner gate structure disposed between the lower pattern and the sheet pattern and between adjacent sheet patterns, and including the gate electrode and the gate insulating film. The above source/drain pattern contacts the gate insulating film of the inner gate structure, and The above sheet pattern includes the first sheet pattern and the second sheet pattern closest to each other in the second direction, and The first sheet pattern is located at the top of the plurality of sheet patterns, and Each of the above-mentioned first sheet pattern and the above-mentioned second sheet pattern includes a side wall in contact with the source/drain pattern, and The sign of the slope of the sidewall of the first sheet pattern is opposite to the sign of the slope of the sidewall of the second sheet pattern, and Each of the above-mentioned first sheet pattern and the above-mentioned second sheet pattern includes an upper surface and a lower surface opposite in the above-mentioned second direction, and The lower surface of the first sheet pattern faces the upper surface of the second sheet pattern, A semiconductor device in which the point where the width of the source/drain pattern in the first direction is maximum is located between the lower surface of the first sheet pattern and the upper surface of the second sheet pattern.

Description

Semiconductor device The present invention relates to a semiconductor device, and more specifically, to a semiconductor device comprising an MBCFET ™ (Multi-Bridge Channel Field Effect Transistor). As one of the scaling techniques to increase the density of semiconductor devices, a multi-gate transistor has been proposed in which a multi-channel active pattern (or silicon body) in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the multi-channel active pattern. Since these multi-gate transistors utilize a three-dimensional channel, they are easy to scale. In addition, current control capability can be improved without increasing the gate length of the multi-gate transistor. Furthermore, the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed. Patent Document 1 discloses a semiconductor device that uses a multi-channel active pattern as a channel region. [Prior Art Literature] Patent Document 1: U.S. Registered Patent Publication US10,431,661 (Oct. 01, 2019) delete FIG. 1 is an exemplary plan view for illustrating a semiconductor device according to some embodiments. Figures 2 and 3 are cross-sectional views taken along A-A and B-B of Figure 1. Figure 4 is a drawing showing an enlarged view of the P area of Figure 2. Figures 5 to 7 are enlarged drawings of section Q of Figure 4. FIG. 8 is a drawing for illustrating a semiconductor device according to some embodiments. FIG. 9 is a drawing for illustrating a semiconductor device according to some embodiments. FIGS. 10 and FIGS. 11 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 12 and FIGS. 13 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 14 and FIGS. 15 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 16 to 18 are drawings for illustrating semiconductor devices according to several embodiments. FIGS. 19 to 21 are drawings for illustrating a semiconductor device according to some embodiments. In this specification, although terms such as "first," "second," etc. are used to describe various elements or components, it is understood that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Therefore, it is understood that the first element or component mentioned below may be the second element or component within the technical scope of the present invention. Semiconductor devices according to some embodiments may include fin-type transistors (FinFETs), tunneling transistors, three-dimensional (3D) transistors, or vertical transistors (Vertical FETs). Semiconductor devices according to some embodiments may include planar transistors. Additionally, the technical concept of the present invention may be applied to transistors based on two-dimensional materials (2D material-based FETs) and heterostructures thereof. In addition, semiconductor devices according to some embodiments may include bipolar junction transistors, horizontal dual diffusion transistors (LDMOS), etc. With reference to FIGS. 1 to 7, a semiconductor device according to some embodiments will be described. FIG. 1 is an exemplary plan view for illustrating a semiconductor device according to some embodiments. FIG. 2 and FIG. 3 are cross-sectional views taken along A-A and B-B of FIG. 1. FIG. 4 is an enlarged view of region P of FIG. 2. FIG. 5 through 7 are enlarged views of portion Q of FIG. 4. For reference, FIG. 1 is briefly illustrated excluding the first gate insulating film (130), the first source/drain contact (180), the source/drain etching stop film (185), the interlayer insulating film (190, 191), the wiring structure (205), etc. Referring to FIGS. 1 to 7, a semiconductor device according to some embodiments may include a first active pattern (AP1), a plurality of first gate electrodes (120), a plurality of first gate structures (GS1), and a first source/drain pattern (150). The substrate (100) may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate (100) may be a silicon substrate or may include other materials, such as silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto. The first active pattern (AP1) can be placed on the substrate (100). The first active pattern (AP1) can be extended in a first direction (D1). For example, the first active pattern (AP1) can be placed in an area where a PMOS is formed. The first active pattern (AP1) may be, for example, a multi-channel active pattern. The first active pattern (AP1) may include a first sub-pattern (BP1) and a plurality of first sheet patterns (NS1). The first lower pattern (BP1) may protrude from the substrate (100). The first