Search

KR-102963041-B1 - A SEMICONDUCTOR DEVICE

KR102963041B1KR 102963041 B1KR102963041 B1KR 102963041B1KR-102963041-B1

Abstract

The present invention relates to a semiconductor device with improved performance and reliability. The semiconductor device of the present invention comprises a substrate, an active pattern extending in a first direction on the substrate, a plurality of gate electrodes covering the active pattern and extending in a second direction, a gate spacer on the sidewall of the plurality of gate electrodes, a source/drain pattern between the plurality of gate electrodes, a sidewall of the gate spacer, and an etch stop film disposed along the profile of the source/drain pattern, an interlayer insulating film disposed between the plurality of gate electrodes and including a contact trench exposing the source/drain pattern, a liner film disposed on the outer wall of the contact trench, and a source/drain contact on the liner film that fills the contact trench and is connected to the source/drain pattern, wherein at least a portion of the liner film is disposed within the source/drain pattern.

Inventors

  • 유우경
  • 강상구
  • 이준채
  • 류경민
  • 이우진

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260508
Application Date
20221213

Claims (10)

  1. Substrate; On the substrate, an active pattern extending in a first direction; A plurality of gate electrodes covering the above active pattern and extending in a second direction; Gate spacers on the sidewalls of the plurality of gate electrodes; Source/drain pattern between the plurality of gate electrodes above; A gate capping film disposed on each of the above plurality of gate electrodes; An etch stop film disposed along the sidewall of the gate spacer and the profile of the source/drain pattern; An interlayer insulating film disposed between the plurality of gate electrodes and including a contact trench exposing the source/drain pattern; A liner membrane disposed on the outer wall of the above contact trench; and On the liner film, a source/drain contact is included that fills the contact trench and is connected to the source/drain pattern. The above etch stop layer is not placed on the sidewall of the gate capping layer, and A semiconductor device in which at least a portion of the above liner film is disposed within the above source/drain pattern.
  2. delete
  3. In Article 1, A semiconductor device in which, based on the upper surface of the substrate, the level of the bottom surface of the source/drain contact is lower than the level of the bottom surface of the liner film.
  4. Substrate; On the substrate, an active pattern extending in a first direction; A plurality of gate electrodes covering the above active pattern and extending in a second direction; A plurality of gate spacers on the sidewalls of each of the above plurality of gate electrodes; A first gate capping film on the plurality of gate electrodes and the plurality of gate spacers; Source/drain pattern between the plurality of gate electrodes above; An etch stop film disposed along the sidewalls of the plurality of gate spacers and the profile of the source/drain pattern; A liner film extending along the profile of the etch stop film, the sidewall of the first gate capping film, and the upper surface of the first gate capping film, with at least a portion disposed within the source/drain pattern; On the liner film, a second gate capping film that overlaps with the first gate capping film in a third direction; and Between the plurality of gate electrodes, a source/drain contact connected to the source/drain pattern is included, and A semiconductor device in which the above liner film comprises an oxide-based insulating material.
  5. In Paragraph 4, A semiconductor device in which the upper surface of the second gate capping film is placed in the same plane as the upper surface of the source/drain contact.
  6. In Paragraph 4, A semiconductor device in which the thickness of the above liner film is constant.
  7. In Paragraph 4, A semiconductor device in which the above liner film is not disposed on the sidewall of the above second gate capping film.
  8. In Paragraph 4, A semiconductor device in which the above-mentioned etch stop layer comprises a nitride-based insulating material.
  9. In Paragraph 4, The above active pattern includes a lower pattern and at least one sheet pattern on the lower pattern, and A semiconductor device in which at least one sheet pattern is in contact with the source/drain pattern.
  10. Substrate; An active pattern on the substrate, comprising a lower pattern extending in a first direction and at least one sheet pattern spaced apart from the lower pattern in a third direction; A field insulating film covering the sidewall of the lower pattern above; A plurality of gate electrodes extending in a second direction, wrapping the sheet pattern on the lower pattern; A plurality of gate spacers on the sidewalls of each of the above plurality of gate electrodes; A plurality of gate capping films disposed on each of the above plurality of gate electrodes; A source/drain pattern connected to at least one sheet pattern between each of the plurality of gate electrodes; An etch stop film disposed along the upper surface of the field insulating film, the sidewalls of each of the plurality of gate spacers, and the profile of the source/drain pattern; An interlayer insulating film disposed between the plurality of gate electrodes and including a contact trench exposing the source/drain pattern; A liner membrane disposed on the outer wall of the above contact trench; and On the liner film, a source/drain contact is included that fills the contact trench and is connected to the source/drain pattern. With respect to the upper surface of the substrate, the level of the bottom surface of the source/drain contact is lower than the level of the bottom surface of the liner film, and The above etch stop layer is not disposed on the sidewalls of the plurality of gate capping layers, and The above etch stop layer comprises a nitride-based insulating material, and The above liner film comprises an oxide-based insulating material, and A semiconductor device in which at least a portion of the above liner film is in contact with the above source/drain pattern.

Description

A semiconductor device The present invention relates to a semiconductor device. As one of the scaling techniques to increase the density of semiconductor devices, a multi-gate transistor has been proposed in which a multi-channel active pattern (or silicon body) in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the multi-channel active pattern. Since these multi-gate transistors utilize a three-dimensional channel, they are easy to scale. In addition, current control capability can be improved without increasing the gate length of the multi-gate transistor. Furthermore, the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed. Meanwhile, as the pitch size of semiconductor devices decreases, research is needed to reduce capacitance and ensure electrical stability between contacts within the semiconductor device. FIG. 1 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 2 is an exemplary cross-sectional view taken along line AA of FIG. 1. FIG. 3 is an exemplary cross-sectional view taken along the BB line of FIG. 1. Figure 4 is an exemplary cross-sectional view taken along the CC line of Figure 1. FIGS. 5 to 8 are drawings for illustrating semiconductor devices according to several other embodiments. FIGS. 9 and FIGS. 10 are drawings for illustrating a semiconductor device according to several other embodiments. FIGS. 11 and FIGS. 12 are drawings for illustrating a semiconductor device according to several other embodiments. FIGS. 13 to 17 are drawings for illustrating semiconductor devices according to several other embodiments. FIGS. 18 to 27 are intermediate drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. In this specification, although terms such as first, second, upper, and lower are used to describe various elements or components, it is understood that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Accordingly, it is understood that the first element or component mentioned below may be the second element or component within the technical scope of the present invention. Furthermore, it is understood that the lower element or component mentioned below may be the upper element or component within the technical scope of the present invention. In the drawings relating to semiconductor devices according to some embodiments, fin-type transistors (FinFETs) including a channel region with a fin-shaped pattern, transistors including nanowires or nanosheets, MBCFET ™ (Multi-Bridge Channel Field Effect Transistor), or vertical transistors (Vertical FETs) are illustrated as examples, but are not limited thereto. Semiconductor devices according to some embodiments may include tunneling transistors or three-dimensional (3D) transistors. Semiconductor devices according to some embodiments may include planar transistors. Additionally, the technical concept of the present invention may be applied to transistors based on two-dimensional materials (2D material-based FETs) and heterostructures thereof. In addition, semiconductor devices according to some embodiments may include bipolar junction transistors, horizontal dual diffusion transistors (LDMOS), etc. Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the attached drawings. First, with reference to FIGS. 1 to 4, a semiconductor device according to some embodiments will be described. FIG. 1 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 2 is an exemplary cross-sectional view cut along line A-A of FIG. 1. FIG. 3 is an exemplary cross-sectional view cut along line B-B of FIG. 1. FIG. 4 is an exemplary cross-sectional view cut along line C-C of FIG. 1. For convenience of explanation, via plugs (210) and wiring lines (220) are not shown in FIG. 1. For reference, in FIG. 2, a via plug (210) connected to a first source/drain contact (170) and a via plug (210) connected to a gate contact (180) are shown arranged adjacently in a first direction (X) on a first active pattern (AP1). However, such arrangement of via plugs (210) is for convenience of explanation only and is not limited thereto. Although not illustrated, a cross-sectional view cut along the second active pattern (AP2) in the first direction (X) may be similar to FIG. 2, except for the location of the via plug (210) and wiring line (220). Referring to FIGS. 1 to 4, a semiconductor device according to some embodiments may include at least one first active pattern (AP1), at least one second active pattern (AP2), a plurality of gate electrodes (120), a first source/drain contact (170), a second source/drain contact (270), and gate contacts (180, 280). The