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KR-102963047-B1 - Semiconductor device

KR102963047B1KR 102963047 B1KR102963047 B1KR 102963047B1KR-102963047-B1

Abstract

The present invention provides a semiconductor device capable of improving device performance and reliability. The semiconductor device comprises an active pattern including a lower pattern extending in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction. The sheet pattern comprises an active pattern including an uppermost sheet pattern, a plurality of gate structures spaced apart in a first direction on the lower pattern and including a gate electrode and a gate insulating film, and a source/drain pattern disposed between adjacent gate structures and including a semiconductor liner film and a semiconductor filling film on the semiconductor liner film. The gate structure comprises an inner gate structure disposed between the lower pattern and the sheet pattern and between adjacent sheet patterns, and including a gate electrode and a gate insulating film. The semiconductor liner film comprises silicon-germanium and contacts the gate insulating film of the inner gate structure, and a portion of the semiconductor liner film protrudes in a first direction above the upper surface of the uppermost sheet pattern.

Inventors

  • 김다혜
  • 김진범
  • 김겸
  • 김영광
  • 전경빈

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260508
Application Date
20221027

Claims (10)

  1. An active pattern comprising a lower pattern extended in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction, wherein the sheet patterns include an uppermost sheet pattern; A plurality of gate structures spaced apart in the first direction and disposed on the lower pattern above, and comprising a gate spacer, a gate electrode, and a gate insulating film; and A source/drain pattern disposed between adjacent gate structures and comprising a semiconductor liner film and a semiconductor filling film on the semiconductor liner film, and The gate structure comprises an inner gate structure disposed between the lower pattern and the sheet pattern and between adjacent sheet patterns, and including the gate electrode and the gate insulating film. The semiconductor liner film comprises silicon-germanium and is in contact with the gate insulating film of the inner gate structure, and The gate spacer includes an inner wall facing the side wall of the gate electrode, an outer wall opposite to the inner wall of the gate spacer, and a connecting side wall connecting the inner wall of the gate spacer and the outer wall of the gate spacer. The semiconductor liner film comprises a first horizontal portion in contact with the sheet pattern and a second horizontal portion disposed between the first horizontal portion and the semiconductor filling film. From a planar perspective, the first horizontal portion contacts the connecting side wall of the gate spacer, and the second horizontal portion contacts the outer wall of the gate spacer, and A semiconductor device in which a portion of the above semiconductor liner film protrudes in the first direction above the upper surface of the above top sheet pattern.
  2. In Article 1, The semiconductor liner film includes an outer surface in contact with the sheet pattern and an inner surface facing the semiconductor filling film. The liner recess defined by the inner surface of the semiconductor liner film includes a plurality of width-extended regions, and A semiconductor device in which, as it moves away from the upper surface of the lower pattern, the width of each width expansion region in the first direction increases and then decreases.
  3. In Article 2, A semiconductor device in which the point where the width of the width expansion area in the first direction is maximum is located between the lower pattern and the sheet pattern, and between the sheet pattern adjacent in the second direction.
  4. In Article 1, The semiconductor liner film includes an outer surface in contact with the sheet pattern and an inner surface facing the semiconductor filling film. A semiconductor device in which the width of a liner recess defined by the inner surface of the semiconductor liner film increases and then decreases as it moves away from the upper surface of the lower pattern.
  5. In Article 1, The above semiconductor liner film is a semiconductor device that extends along a portion of the outer wall of the gate spacer.
  6. In Article 5, A semiconductor device that, from a planar perspective, has a semiconductor liner covering a portion of the outer wall of the gate spacer and contacting the outer wall of the gate spacer.
  7. In Article 1, The inner surface of the semiconductor liner film is in contact with the semiconductor filling film of the semiconductor device.
  8. In Article 1, The above source/drain pattern further includes a semiconductor insertion film continuously formed along the inner surface of the semiconductor liner film, and The above semiconductor insertion film comprises silicon germanium, and A semiconductor device in which the germanium fraction of the semiconductor insertion film is greater than the germanium fraction of the semiconductor liner film and smaller than the germanium fraction of the semiconductor filling film.
  9. An active pattern comprising a lower pattern extended in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction, wherein the sheet patterns include an uppermost sheet pattern; A plurality of gate structures spaced apart in the first direction and disposed on the lower pattern above, and comprising a gate spacer, a gate electrode, and a gate insulating film; and A source/drain pattern disposed between adjacent gate structures and comprising a semiconductor liner film and a semiconductor filling film on the semiconductor liner film, and The gate spacer includes an inner wall facing the side wall of the gate electrode, an outer wall opposite to the inner wall of the gate spacer, and a connecting side wall connecting the inner wall of the gate spacer and the outer wall of the gate spacer. The semiconductor liner film comprises a first horizontal portion in contact with the sheet pattern and a second horizontal portion disposed between the first horizontal portion and the semiconductor filling film. The semiconductor liner film and the semiconductor filling film comprise silicon-germanium, and The fraction of germanium in the semiconductor liner film is smaller than the fraction of germanium in the semiconductor filling film, and The height from the upper surface of the lower pattern to the upper surface of the uppermost sheet pattern is smaller than the height from the upper surface of the lower pattern to the uppermost part of the semiconductor liner, and From a planar perspective, the first horizontal portion contacts the connecting side wall of the gate spacer, and the second horizontal portion contacts the outer wall of the gate spacer, and From a planar perspective, the semiconductor liner is a semiconductor device that covers a portion of the outer wall of the gate spacer.
  10. An active pattern comprising a lower pattern extended in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction, wherein the sheet patterns include an uppermost sheet pattern; A plurality of gate structures spaced apart in the first direction and disposed on the lower pattern above, and comprising a gate spacer, a gate electrode, and a gate insulating film; and A source/drain pattern disposed between adjacent gate structures and comprising a semiconductor liner film and a semiconductor filling film on the semiconductor liner film, and The gate spacer includes an inner wall facing the side wall of the gate electrode, an outer wall opposite to the inner wall of the gate spacer, and a connecting side wall connecting the inner wall of the gate spacer and the outer wall of the gate spacer. The semiconductor liner film comprises a first horizontal portion in contact with the sheet pattern and a second horizontal portion disposed between the first horizontal portion and the semiconductor filling film. From a planar perspective, the first horizontal portion contacts the connecting side wall of the gate spacer, and the second horizontal portion contacts the outer wall of the gate spacer, and The height from the upper surface of the lower pattern to the upper surface of the uppermost sheet pattern is smaller than the height from the upper surface of the lower pattern to the uppermost part of the semiconductor liner, and The semiconductor liner film and the semiconductor filling film comprise silicon-germanium, and The fraction of germanium in the semiconductor liner film is smaller than the fraction of germanium in the semiconductor filling film, and The semiconductor liner film includes an outer surface in contact with the sheet pattern and an inner surface facing the semiconductor filling film. The liner recess defined by the inner surface of the semiconductor liner film includes a plurality of width-extended regions, and A semiconductor device in which, as it moves away from the upper surface of the lower pattern, the width of each of the width expansion regions in the first direction increases and then decreases.

Description

Semiconductor device The present invention relates to a semiconductor device, and more specifically, to a semiconductor device comprising an MBCFET ™ (Multi-Bridge Channel Field Effect Transistor). As one of the scaling techniques to increase the density of semiconductor devices, a multi-gate transistor has been proposed in which a multi-channel active pattern (or silicon body) in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the multi-channel active pattern. Since these multi-gate transistors utilize a three-dimensional channel, they are easy to scale. In addition, current control capability can be improved without increasing the gate length of the multi-gate transistor. Furthermore, the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed. FIG. 1 is an exemplary plan view for illustrating a semiconductor device according to some embodiments. Figures 2 and 3 are cross-sectional views taken along A-A and B-B of Figure 1. Figure 4 is a top view taken by cutting along C-C of Figure 2. Figures 5 and 6 are top views cut along D-D of Figure 2. Figure 7 is a diagram illustrating the shape of the semiconductor liner film of Figure 2. FIGS. 8 to 10 are drawings showing enlarged views of the P area of FIG. 2, respectively. FIG. 11 is a diagram illustrating the germanium fraction of the first source/drain pattern of FIG. 2. FIGS. 12 to 16 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 17 and FIGS. 18 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 19 and FIGS. 20 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 21 and FIGS. 22 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 23 and FIGS. 24 are drawings for illustrating a semiconductor device according to some embodiments. FIG. 25 is a drawing for illustrating a semiconductor device according to some embodiments. FIGS. 26 and FIGS. 27 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 28 to 30 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 31 to 38 are intermediate drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. In this specification, although terms such as "first," "second," etc. are used to describe various elements or components, it is understood that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Therefore, it is understood that the first element or component mentioned below may be the second element or component within the technical scope of the present invention. Semiconductor devices according to some embodiments may include fin-type transistors (FinFETs), tunneling transistors, three-dimensional (3D) transistors, or vertical transistors (Vertical FETs). Semiconductor devices according to some embodiments may include planar transistors. Additionally, the technical concept of the present invention may be applied to transistors based on two-dimensional materials (2D material-based FETs) and heterostructures thereof. In addition, semiconductor devices according to some embodiments may include bipolar junction transistors, horizontal dual diffusion transistors (LDMOS), etc. With reference to FIGS. 1 to 10, a semiconductor device according to some embodiments will be described. FIG. 1 is an exemplary plan view for illustrating a semiconductor device according to some embodiments. FIG. 2 and FIG. 3 are cross-sectional views taken along A-A and B-B of FIG. 1. FIG. 4 is a top view taken along C-C of FIG. 2. FIG. 5 and FIG. 6 are top views taken along D-D of FIG. 2. FIG. 7 is a drawing for illustrating the shape of the semiconductor liner film of FIG. 2. FIG. 8 through FIG. 10 are enlarged drawings of region P of FIG. 2, respectively. FIG. 11 is a drawing for illustrating the germanium fraction of the first source/drain pattern of FIG. 2. For reference, FIG. 1 is briefly illustrated excluding the first gate insulating film (130), the first source/drain contact (180), the source/drain etching stop film (185), the interlayer insulating film (190, 191), the wiring structure (205), etc. Referring to FIGS. 1 to 11, a semiconductor device according to some embodiments may include a first active pattern (AP1), a plurality of first gate electrodes (120), a plurality of first gate structures (GS1), and a first source/drain pattern (150). The substrate (100) may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate (100) may be a silicon substrate or may include other materials, such as silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium ars