KR-102963066-B1 - Dynamic over-provisioning allocation for usage blocks

KR102963066B1KR 102963066 B1KR102963066 B1KR 102963066B1KR-102963066-B1

Abstract

One or more blocks from a pool of storage area blocks of a memory component are allocated to a first set of use blocks. A first write operation is performed to write first data from a user block of the memory component to a first data stripe. It is determined whether the blocks within the first set of use blocks satisfy the condition that the first set of use blocks will be discarded. In response that the blocks within the first set of use blocks satisfy the condition, one or more other blocks from a pool of storage area blocks of the memory component are allocated to a second set of use blocks. A second write operation is performed to write second data from a user block of the memory component to a second data stripe.

Inventors

무체를라, 키쇼어 쿠마르
신기디, 하리쉬 알.
말쉬, 아슈토쉬
레야프로루, 밤시 파반
라트남, 삼파쓰 케이.

Assignees

마이크론 테크놀로지, 인크.

Dates

Publication Date: 20260513
Application Date: 20201106
Priority Date: 20191108

Claims (20)

In the system, Memory components; and A processing device operably coupled with the above-mentioned memory component, Allocating one or more blocks from a pool of storage area blocks of the above memory component to a first set of purposed blocks; In the user blocks of the memory component, first plurality of write operations are performed to write first data to first plurality of data stripes, and the first set of purpose blocks is for storing purposed data of the first plurality of data stripes associated with the first plurality of write operations; Determining whether the blocks within the first set of use blocks satisfy a condition indicating that the use blocks of the first set of use blocks will be retired; In response to the blocks within the first set of use blocks satisfying the condition, it is determined that the blocks within the first set of use blocks should be discarded, and one or more other blocks from the pool of storage area blocks of the memory component are allocated to the second set of use blocks; and A system comprising a processing device, wherein the user blocks of the memory component perform a second plurality of write operations for writing second data to a second plurality of data stripes, and the second set of use blocks are for storing use data of the second plurality of data stripes associated with the second plurality of write operations.
In claim 1, to perform the first plurality of write operations for writing the first data to the first plurality of data stripes in the user blocks of the memory component, the processing device, A first recording operation of the first plurality of recording operations is performed to record a first portion of the first data in the data stripes of the first plurality of data stripes in the user blocks of the memory component, and the parity data of the data stripes of the first plurality of data stripes is stored in the usage blocks of the first set; Verify that there are no uncorrectable bit errors in the data stripes of the first plurality of data stripes recorded in the user blocks of the memory component; In response to verifying that there are no uncorrectable bit errors in the data stripes of the first plurality of data stripes recorded in the user blocks of the memory component, an erasure operation is performed to erase the first set of usage blocks; and A system that performs a second recording operation of the first plurality of recording operations in the user blocks of the memory component, which records a second part of the first data in another data stripe among the first plurality of data stripes, and stores the parity data of the other data stripe in the first set of usage blocks following the performance of an erasure operation in the first set of usage blocks.
A system according to claim 1, wherein the user blocks of the memory component on which the first plurality of data stripes and the second plurality of data stripes are recorded operate in multi-bit mode, and the blocks within the first set of use blocks and other blocks within the second set of use blocks operate in single-bit mode or multi-bit mode.
In paragraph 3, the over-provisioning blocks within the pool of storage area blocks are a system operating in the multi-bit mode or single-bit mode.
In claim 1, to determine whether the blocks within the use blocks of the first set satisfy the condition, the processing device, Determining the RBER (raw bit error rate) associated with the use blocks of the first set above; Determining whether the RBER associated with the above-mentioned first set of use blocks satisfies a threshold; and A system that discards the first set of use blocks in response to the fact that the RBER associated with the first set of use blocks satisfies the threshold.
A system according to claim 1, wherein the first plurality of write operations for writing the first data to the first plurality of data stripes in the user blocks of the memory component and the second plurality of write operations for writing the second data to the second plurality of data stripes in the user blocks of the memory component are RAIN operations for writing a plurality of RAIN (redundant array of independent NAND) stripes.
A system according to claim 1, wherein the first set of use blocks comprises a minimum number of use blocks capable of storing use data for a maximum number of open user blocks at any given time, and the first set of use blocks comprises a number of use blocks less than the total number of use blocks used over the lifetime of the memory component.
In the system, Memory components; and A processing device operably coupled with the above-mentioned memory component, Allocating one or more blocks from a pool of over-provisioning blocks of the above memory component to a first set of parity blocks; First plurality of write operations are performed in the user blocks of the memory component to write first data to first plurality of data stripes, and the first set of parity blocks stores parity data of the first plurality of data stripes associated with the first plurality of write operations; Determining whether the user blocks of the above memory component satisfy a threshold corresponding to the endurance state of the user blocks; In response to the determination that the user blocks of the memory component satisfy a threshold corresponding to the durability state of the user blocks, allocate at least the number of blocks equal to the remainder of the parity blocks among the total number of parity blocks used during the lifetime of the memory component to a second set of parity blocks from the pool of over-provisioning blocks; and A system comprising a processing device, wherein the processing device performs second plurality of write operations for writing second data to second plurality of data stripes in user blocks of the memory component, and the second set of parity blocks stores parity data of the second plurality of data stripes associated with the second plurality of write operations.
In paragraph 8, in order to allocate one or more blocks from a pool of over-provisioning blocks of the memory component to the first set of parity blocks, the processing device, A system that allocates from the over-provisioning block pool a number of blocks equal to the minimum number of parity blocks capable of storing parity data for the maximum number of open user blocks at any given time.
In paragraph 9, the processing device further comprises, Determining whether the parity blocks of the first set satisfy a condition indicating that the parity blocks of the first set should be discarded; In response to the determination that the first set of parity blocks satisfies the condition, indicate that the blocks within the first set of parity blocks will be discarded and allocate one or more blocks from the pool of over-provisioning blocks of the memory component to the third set of parity blocks; and A system that performs third plurality of write operations to write third data to third plurality of data stripes in user blocks of a memory component, and the third set of parity blocks stores parity data of third plurality of data stripes associated with the third plurality of write operations.
In paragraph 10, to determine whether the first set of parity blocks satisfies a condition indicating that the first set of parity blocks should be discarded, the processing device, Determining the RBER (raw bit error rate) associated with the first set of parity blocks; Determining whether the RBER associated with the first set of parity blocks satisfies a threshold; and A system that discards the first set of parity blocks in response to the fact that the RBER associated with the first set of parity blocks satisfies the threshold.
In paragraph 8, in order to allocate one or more blocks from the pool of over-provisioning blocks of the memory component to the first set of parity blocks, the processing device, A system that allocates from the over-provisioning block pool a number of blocks greater than the minimum number of parity blocks capable of storing parity data for a maximum number of open user blocks at any given time and less than the total number of parity blocks to be used during the lifetime of the memory component.
In claim 8, in order to perform the first plurality of write operations for writing the first data to the first plurality of data stripes in the memory component, the processing device, A first recording operation of the first plurality of recording operations is performed to record a first portion of the first data in the data stripes of the first plurality of data stripes in the user blocks of the memory component, and the parity data of the data stripes of the first plurality of data stripes is stored in the first set of parity blocks; Verify that there are no uncorrectable bit errors in the data stripes of the first plurality of data stripes recorded in the user blocks of the memory component; In response to verifying that there are no uncorrectable bit errors in the data stripes of a plurality of data stripes recorded in the user blocks of the memory component, an erasure operation is performed to erase the first set of parity blocks; and A system that performs a second recording operation of the first plurality of recording operations, which records a second portion of the first data to another data strip of the first plurality of data strips in the user blocks of the memory component, and stores the parity data of the other data strip in the first set of parity blocks after performing an erasure operation in the first set of parity blocks.
A system according to claim 8, wherein the user blocks of the memory component on which the first data among the first plurality of data stripes and the second data among the second plurality of data stripes are recorded operate in a multi-bit mode, the blocks of the first set of parity blocks and the blocks of the second set of parity blocks operate in a single-bit mode, and the pool of over-provisioning blocks operates in the multi-bit mode.
In claim 8, the first plurality of write operations for writing the first data to the first plurality of data stripes in the user blocks of the memory component and the second plurality of write operations for writing the second data to the second plurality of data stripes in the user blocks of the memory component are RAIN operations for writing a plurality of RAIN (redundant array of independent NAND) stripes, a system.
In claim 8, the system comprises parity blocks of the first set less than the total number of parity blocks used during the lifetime of the memory component.
In terms of method, A step of allocating one or more blocks from a pool of storage area blocks of a memory component to a first set of use blocks by a processing device; A step of performing first plurality of write operations for writing first data to first plurality of data stripes in user blocks of the memory component, wherein the first set of use blocks stores use data of the first plurality of data stripes associated with the first plurality of write operations; A step of determining whether the blocks within the first set of use blocks satisfy a condition indicating that the use blocks of the first set of use blocks will be discarded; In response to the fact that the blocks in the first set of use blocks satisfy the condition, determining that the blocks in the first set of use blocks should be discarded, and allocating one or more other blocks from the pool of storage area blocks of the memory component to the second set of use blocks; and A method comprising the step of performing second plurality of write operations for writing second data to second plurality of data stripes in user blocks of the memory component, wherein the second set of use blocks stores use data of the second plurality of data stripes associated with the second plurality of write operations.
In claim 17, the step of performing the first plurality of write operations for writing the first data to the first plurality of data stripes in the user blocks of the memory component is A step of performing a first recording operation among the first plurality of recording operations for recording a first portion of the first data into the data strips of the first plurality of data strips in the user blocks of the memory component, wherein the parity data of the data strips of the first plurality of data strips is stored in the first set of usage blocks; A step of verifying that there are no uncorrectable bit errors in the data stripes of the first plurality of data stripes recorded in the user blocks of the memory component; A step of performing an erasure operation to erase the first set of usage blocks in response to verifying that there are no uncorrectable bit errors in the data stripes of the first plurality of data stripes recorded in the user blocks of the memory component; and A method comprising the step of performing a second recording operation among the first plurality of recording operations of recording a second part of the first data to another data stripe among the first plurality of data stripes in the user blocks of the memory component, wherein the parity data of the other data stripe is stored in the first set of use blocks following the erasure operation in the first set of use blocks.
A method according to claim 17, wherein the user blocks of the memory component on which the first plurality of data stripes and the second plurality of data stripes are recorded operate in a multi-bit mode, the blocks in the first set of use blocks and other blocks in the second set of use blocks operate in a single-bit mode or a multi-bit mode, and the over-provisioning blocks in the pool of storage area blocks operate in the multi-bit mode or a single-bit mode.
In claim 17, the step of determining whether the blocks within the use blocks of the first set satisfy the condition is, A step of determining the RBER (raw bit error rate) associated with the use blocks of the first set above; A step of determining whether the RBER associated with the first set of use blocks satisfies a threshold; and A method comprising the step of discarding the first set of use blocks in response to the fact that the RBER associated with the first set of use blocks satisfies a threshold.

Description

Dynamic over-provisioning allocation for usage blocks The embodiments of the present disclosure generally relate to memory subsystems, and more specifically, to the dynamic allocation of one or more blocks from a pool of storage area blocks of a memory component for use as purposed blocks. A memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. Generally, a host system may use the memory subsystem to store data in memory components and to retrieve data from memory components. The present disclosure will be more fully understood from the detailed description set forth below and the accompanying drawings of various embodiments of the present disclosure. FIG. 1a illustrates an exemplary computing environment including a memory subsystem according to some embodiments of the present disclosure. FIG. 1b illustrates blocks of a memory subsystem according to embodiments of the present disclosure. FIG. 1c illustrates a data stripe according to an embodiment of the present disclosure. FIG. 2a is a flowchart of an exemplary method for allocating one or more blocks from a pool of storage area blocks to be used as use blocks according to some embodiments of the present disclosure. FIG. 2b is a flowchart of an exemplary method for allocating one or more blocks from a pool of over-provisioning blocks to be used as parity blocks according to some embodiments of the present disclosure. FIG. 3 is a diagram illustrating the full dynamic allocation of one or more blocks from a pool of storage area blocks to be used as use blocks according to some embodiments of the present disclosure. FIG. 4 is a diagram illustrating the partial dynamic allocation of one or more blocks from a pool of storage area blocks to be used as use blocks according to some embodiments of the present disclosure. FIG. 5 is a diagram illustrating a multi-phase dynamic allocation of one or more blocks from a pool of storage area blocks to be used as use blocks according to some embodiments of the present disclosure. FIG. 6 illustrates an exemplary machine of a computer system in which a set of instructions for causing the machine to perform any one or more of the operations discussed in this specification can be executed. Aspects of the present disclosure relate to the dynamic allocation of one or more blocks from a pool of storage area blocks of a memory component for use as application blocks. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices and memory modules are described below in relation to FIG. 1. Generally, a host system may utilize a memory subsystem comprising one or more memory devices for storing data. The host system may provide data to be stored in the memory subsystem and may request data to be retrieved from the memory subsystem. A memory device can be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND (negative-AND) devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells that store data bits. For some memory devices, such as NAND devices, blocks are the smallest area that can be erased, and the pages within the blocks cannot be erased individually. For these devices, erase operations are performed one block at a time. Pages within a block may contain valid data, invalid data, or no data. Invalid data is data that has been marked as old as a new version of data is stored in the memory device. Valid data is the most recent version of this data stored in the memory device. The memory subsystem may mark data as invalid based on information received, for example, from the operating system. A block may have some pages containing valid data and some pages containing invalid data. An algorithm referred to as "garbage collection" below may be invoked to allow the block to be erased and reused for write operations, so as not to wait for all pages within the block to contain invalid data in order to erase and reuse the block. Garbage collection is a set of operations including, for example, selecting a block containing valid and invalid data; selecting pages within the block containing valid data; copying valid data to new locations (e.g., free pages within another block); marking the data of the previously selected pages as invalid; and erasing the selected block. Because garbage collection can write valid data to different blocks before a block is erased, data may be rewritten multiple times to different blocks within the memory subsystem. The amount of additional rewriting of data within the memory subsystem is referred to herein as write-amplification. Write-amplification can reduce the operational l