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KR-102963067-B1 - SEMICONDUCTOR DEVICE MANUFACTURING METHOD

KR102963067B1KR 102963067 B1KR102963067 B1KR 102963067B1KR-102963067-B1

Abstract

The present invention relates to a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to the present invention comprises providing a first layer having a first surface, forming a second layer on the first layer that exposes the first surface, the second layer having a second surface that is connected to the first surface and intersects the first surface, forming an inhibitor layer on the first surface and the second surface, selectively removing the inhibitor layer on the second surface to expose the second surface, and forming a layer of interest on the second surface, wherein the physical properties of the first layer and the physical properties of the second layer are different from each other.

Inventors

  • 고은혜
  • 한훈
  • 황병근
  • 문정호
  • 송현지
  • 조윤정

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260508
Application Date
20211109

Claims (10)

  1. A first layer having a first surface is provided, A second layer is formed on the first layer that exposes the first surface, and the second layer is connected to the first surface and has a second surface that intersects the first surface. An inhibitor layer is formed on the first surface and the second surface, and Selectively removing the inhibitor layer on the second surface to expose the second surface, and On the second surface above, a layer of interest is formed, and It includes removing the inhibitor layer on the first surface by acid treatment, and The above inhibitor layer reacts with acid or hydrogen ions to dissociate, and A method for manufacturing a semiconductor device in which the physical properties of the first layer and the physical properties of the second layer are different from each other.
  2. In Article 1, Selectively removing the inhibitor layer on the second surface above utilizes a heat treatment process, and A method for manufacturing a semiconductor device in which the inhibitor layer on the first surface is not removed through the above heat treatment process.
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  5. In Article 1, A method for manufacturing a semiconductor device, wherein the inhibitor layer comprises at least one of hexamethyldisilazane (HMDS), trimethylsilyldiethylamine, bis(N,N-diethylamino)dimethylsilane, trimethylsilyldimethylamine, bis(trimethylsilyl)hydrazine, and trimethylchlorosilane.
  6. In Article 1, A method for manufacturing a semiconductor device, wherein the width of the inhibitor layer is 10 Angstroms or less.
  7. In Article 1, A method for manufacturing a semiconductor device wherein the first layer comprises at least one of titanium nitride, an organic polymer, and a combination thereof.
  8. A gap-fill insulating layer is formed on a titanium nitride layer, and The gap-fill insulating layer is etched in a first direction to form a first gap-fill insulating pattern and a second gap-fill insulating pattern, wherein the first gap-fill insulating pattern includes a first surface facing the second gap-fill insulating pattern, and the second gap-fill insulating pattern includes a second surface facing the first surface. The first gap-fill insulation pattern and the second gap-fill insulation pattern expose the upper surface of the titanium nitride layer, and A first inhibitor layer is formed on the upper surface of the above titanium nitride layer, and A second inhibitor layer is formed on the first surface and the second surface, and The second inhibitor layer is selectively removed through a heat treatment process to expose the first surface and the second surface, and The method includes depositing a layer of interest on the first surface and the second surface in a second direction intersecting the first direction, and A method for manufacturing a semiconductor device in which the above-mentioned layer of interest is not deposited in the first direction on the above-mentioned first inhibitor layer.
  9. A substrate comprising a first region and a second region is provided, and A first sheet pattern is formed on the substrate of the first region, and A second sheet pattern is formed on the substrate of the second region above, and A work function metal layer is formed on the substrate that surrounds the first sheet pattern and the second sheet pattern, and A sacrificial layer covering the first and second sheet patterns is formed on the substrate, and Between the first sheet pattern and the second sheet pattern, a trench penetrating the sacrificial layer is formed, and the trench exposes the work function metal layer. An inhibitor layer is formed on the bottom surface and side surface of the above trench, and The inhibitor layer formed on the side of the trench is selectively removed through a heat treatment process, and the inhibitor layer formed on the bottom surface of the trench is not removed through the heat treatment process. It includes optionally forming a layer of interest on the side of the above trench, A method for manufacturing a semiconductor device, wherein the above work function metal layer comprises titanium nitride.
  10. In Article 9, A method for manufacturing a semiconductor device, further comprising, after forming the layer of interest, selectively removing the work function metal layer overlapping the trench through a wet etching process.

Description

Semiconductor Device Manufacturing Method The present invention relates to a method for manufacturing a semiconductor device, and specifically, to a method for manufacturing a semiconductor device using selective deposition and selective desorption. With the recent rapid proliferation of information media, the capabilities of semiconductor devices are also advancing dramatically. For recent semiconductor products, high integration is required to ensure low costs and high quality in order to secure competitiveness. To achieve this high integration, semiconductor devices are undergoing scaling down. Meanwhile, as pitch size decreases, technologies for electrically isolating integrated devices are becoming increasingly important and active. Isolation technologies used in scaled devices also require ultra-miniaturization. FIG. 1 is an exemplary flowchart for explaining a method for manufacturing a semiconductor device according to some embodiments. FIGS. 2 to 6 are intermediate drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. Figures 7a and 7b are graphs showing the analysis of the first surface and the second surface using X-ray Photoelectron Spectroscopy (XPS) before treatment with the inhibitor layer. Figures 8a and 8b are graphs showing the analysis of the first surface and the second surface using X-ray Photoelectron Spectroscopy (XPS) when the inhibitor layer treatment was performed for 1 minute. Figures 9a and 9b are graphs showing the analysis of the first surface and the second surface using X-ray Photoelectron Spectroscopy (XPS) when the inhibitor layer treatment was performed for 3 minutes. Figures 10a and 10b are graphs showing the analysis of the first surface and the second surface using X-ray Photoelectron Spectroscopy (XPS) when the heat treatment process was performed for 1 minute. Figures 11a and 11b are graphs showing the analysis of the first surface and the second surface using X-ray Photoelectron Spectroscopy (XPS) when the heat treatment process was performed for 4 minutes. Figure 12 is a graph showing the analysis of the first surface using X-ray Photoelectron Spectroscopy (XPS) when acid treatment was performed. FIGS. 13 to 26 are intermediate drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. Hereinafter, a method for manufacturing a semiconductor device according to several embodiments will be described with reference to FIGS. 1 to 6. FIG. 1 is an exemplary flowchart for illustrating a method for manufacturing a semiconductor device according to some embodiments. FIGS. 2 through 6 are intermediate drawings for illustrating a method for manufacturing a semiconductor device according to some embodiments. Referring to FIGS. 1 and FIGS. 2, a first layer (10) and a second layer (20) may be provided (S100). The first layer (10) may be a titanium nitride layer. That is, the first layer (10) may include, for example, titanium nitride (TiN), an organic polymer, and a combination thereof. The second layer (20) may be a gap-filling insulating film. The second layer (20) may be, for example, a dry etch resistance layer or a wet etch resistance layer, but is not limited thereto. A second layer (20) is formed on the upper surface (10US) of the first layer (10). A portion of the upper surface (10US) of the first layer (10) is in contact with the second layer (20), and another portion of the upper surface (10US) of the first layer (10) may be exposed by the second layer (20). For example, the second layer (20) may include a first sublayer (21) and a second sublayer (22). Although not illustrated, the first sublayer (21) and the second sublayer (22) may be formed by etching the second layer (20) in a second direction (D2). The first sublayer (21) may be a first gap-fill insulation pattern, and the second sublayer (22) may be a second gap-fill insulation pattern. The first sublayer (21) and the second sublayer (22) may be spaced apart from each other in a first direction (D1). The upper surface (10US) of the first layer (10) may be exposed in the space where the first sublayer (21) and the second sublayer (22) are spaced apart. Hereinafter, the exposed upper surface (10US) of the first layer (10) is defined as the first surface. The first sublayer (21) includes a first surface (21SS). The first surface (21SS) of the first sublayer (21) may face the second sublayer (22). The second sublayer (22) includes a second surface (22SS). The second surface (22SS) of the second sublayer (22) may face the first sublayer (21). That is, the first surface (21SS) of the first sublayer (21) and the second surface (22SS) of the second sublayer (22) can face each other. Hereinafter, the first surface (21SS) of the first sublayer (21) and the second surface (22SS) of the second sublayer (22) are defined as the second surface. That is, the first surface (10US) may extend in the first direction (D1), and the second