KR-102963239-B1 - CLOCK RECOVERY CIRCUIOT FOR DISPLAY

Abstract

The present invention discloses a clock recovery circuit of a display that recovers a clock from a clock data signal, wherein the clock recovery circuit comprises: a clock recovery unit that generates delayed clocks using a multi-stage delay chain including differential delay units; and a delay compensator that controls a first delay time of a first delay unit to be equal to a second delay time of a remaining delay unit, and can compensate for the delay time difference between the first delay time and the second delay time.

Inventors

• 이종석
• 김원

Assignees

• 주식회사 엘엑스세미콘

Dates

Publication Date

20260511

Application Date

20211209

Claims (20)

1. A clock detector that receives a clock data signal including a first clock data signal and a second clock data signal in a differential state, detects a first differential clock from the first clock data signal, and detects a second differential clock from the second clock data signal; A voltage-controlled delay unit comprising differential delay units forming a multi-stage delay chain, generating first differential delay clocks and second differential delay clocks by delaying the first differential clock and the second differential clock through the differential delay units, and providing delay clocks corresponding to the first differential delay clocks; and A delay compensator that controls the capacitances of the input sides of the first differential clock and the second differential clock of the first differential delay unit, respectively, to compensate for the delay time difference between the first delay time of the first differential delay unit and the second delay time of the second differential delay unit selected among the remainder; and The above delay compensator is a clock recovery circuit of a display that reduces the capacitances in response to a delay time difference in which the first delay time is slower than the second delay time, and increases the capacitances in response to a delay time difference in which the first delay time is faster than the second delay time.
2. A clock detector that receives a clock data signal including a first clock data signal and a second clock data signal in a differential state, detects a first differential clock from the first clock data signal, and detects a second differential clock from the second clock data signal; A voltage-controlled delay unit comprising differential delay units forming a multi-stage delay chain, generating first differential delay clocks and second differential delay clocks by delaying the first differential clock and the second differential clock through the differential delay units, and providing delay clocks corresponding to the first differential delay clocks; A delay compensator that controls the capacitances of the input sides of the first differential clock and the second differential clock of the first differential delay unit, respectively, to compensate for the delay time difference between the first delay time of the first differential delay unit and the second delay time of the second differential delay unit selected from the remainder; and A delay control unit that outputs a voltage control signal corresponding to the phase difference between a reference clock and a feedback clock; is provided. The above reference clock uses a first delay clock output from a differential delay unit at a preset position, and The above feedback clock utilizes the second delay clock output from the last differential delay unit, and, The above voltage control delay unit controls the delay time of the differential delay units according to the level of the voltage control signal. Display clock restoration circuit.
3. In claim 2, the delay control unit is, A phase detector that outputs an up control signal and a down control signal corresponding to the phase difference between the reference clock and the feedback clock; A charge pump that provides an output voltage by performing a pull-up corresponding to the up control signal or a pull-down corresponding to the down control signal; and A clock recovery circuit for a display comprising: a loop filter that outputs a voltage control signal of a level corresponding to the output voltage.
4. In claim 2, each of the above differential delay units is, A first input circuit that delays the first input and transmits it to the first node; A second input circuit that delays and transmits a second input, which is differential to the first input, to a second node; A differential comparison circuit that compares a first output of a first input circuit applied through the first node and a second output of a second input circuit applied through the second node, and outputs a first differential delay clock and a second differential delay clock in a differential state as a result of the comparison through the first node and the second node; An inverter that outputs the delay clock obtained by inverting the second differential delay clock of the second node; and A control circuit that controls the driving current of the first input circuit and the second input circuit, respectively, in response to the above voltage control signal; is included. If the above differential delay unit is the first differential delay unit, the first input and the second input correspond to the first differential clock and the second differential clock, and, When the above differential delay unit is the above second differential delay unit, the above first input and the above second input are a clock recovery circuit of a display corresponding to the above first differential delay clock and the above second differential delay clock output from the preceding differential delay unit.
5. In claim 1, the delay compensator is, It includes a first capacitor bank and a second capacitor bank coupled to a first input side and a second input side to which the first differential clock and the second differential clock of the first differential delay unit are input; A clock recovery circuit for a display that controls the first capacitor bank and the capacitances of the first capacitor bank in correspondence with the delay time difference so that the first delay time and the second delay time are the same.
6. delete
7. In claim 1, the delay compensator is, A first time digital converter that compares the first differential clock on the input side of the first differential delay unit with the second delay clock on the output side and outputs a first delay value corresponding to the first delay time; A second time digital converter that compares the input-side third delay clock and the output-side fourth delay clock of the second differential delay unit and outputs a second delay value corresponding to the second delay time; A comparator that compares the first delay value and the second delay value and outputs a comparison value corresponding to the delay time difference; and A clock recovery circuit for a display, characterized by comprising: a first capacitor bank and a second capacitor bank, each coupled to a first input side and a second input side, respectively, to which the first differential clock and the second differential clock of the first differential delay unit are input, and which provide a controlled capacitance corresponding to the comparison value.
8. In Article 7, The second differential delay unit of the above multi-stage delay chain is selected as the second differential delay unit, and The above second delay clock is a clock recovery circuit of the display identical to the above third delay clock.
9. In Article 7, The first time digital converter receives the first differential clock as a first start clock and the second delay clock as a first stop clock, and includes a first chain of first unit delay cells that stepwise shift the first start clock and the first stop clock; The second time digital converter receives the third delay clock as a second start clock and the fourth delay clock as a second stop clock, and includes a second chain of second unit delay cells that stepwise shift the second start clock and the second stop clock; Each of the above-mentioned first unit delay cells shifts the first start clock by delaying it further than the first stop clock by a preset unit delay difference time, and outputs a first difference value that determines the phase of the received first start clock based on the received first stop clock; Each of the above-mentioned second unit delay cells receives the third delay clock as a second start clock and receives the fourth delay clock as a second stop clock, shifts the second start clock by delaying it further than the second stop clock by the unit delay difference time, and outputs a second difference value in which the phase of the second start clock is determined based on the second stop clock; The first time digital converter outputs the first difference values as the first delay values; and, The above second time digital converter is a clock recovery circuit of a display that outputs the above second difference values as the above second delay values.
10. In Article 9, The above first unit delay cell is, A first buffer that shifts the above first stop clock by delaying it by a first unit delay time; A second buffer that shifts the first start clock by delaying it by a second unit delay time, which is the sum of the first unit delay time and the unit delay difference time; and A first phase determiner that outputs a first difference value for determining the phase of the first start clock based on the first stop clock: and, The above second unit delay cell is, A third buffer that shifts the second stop clock by delaying it by the first unit delay time; A fourth buffer that shifts the second start clock by delaying it by the second unit delay time; and A clock recovery circuit of a display comprising a second phase determiner that outputs a second difference value for determining the phase of the second start clock based on the second stop clock.
11. In claim 9, the above comparator is, A clock recovery circuit for a display that generates unit comparison values by comparing whether the first difference values and the second difference values are the same, and outputs the unit comparison values as comparison values.
12. In Article 7, A clock restoration circuit for a display, wherein each of the first capacitor bank and the second capacitor bank is configured in parallel and includes a plurality of unit capacitors selectable by the comparison value.
13. A clock recovery unit comprising differential delay units forming a multi-stage delay chain, generating first differential delay clocks and second differential delay clocks by passing a first differential clock and a second differential clock in a differential state through the differential delay units, and generating delay clocks corresponding to the first differential delay clocks; and A delay compensator that controls the first delay time of the first differential delay unit to be equal to the second delay time of the remaining differential delay unit; is provided, The above delay compensator provides a capacitance controlled to compensate for the delay time difference between the first delay time and the second delay time to the input sides of the first differential clock and the second differential clock of the first differential delay unit, respectively, and A clock recovery circuit for a display that reduces the capacitances in response to a delay time difference where the first delay time is slower than the second delay time, and increases the capacitances in response to a delay time difference where the first delay time is faster than the second delay time.
14. In Article 13, Further comprising a delay control unit that outputs a voltage control signal corresponding to the phase difference between a reference clock and a feedback clock; The above reference clock uses a first delay clock output from a differential delay unit at a preset position, and The above feedback clock utilizes the second delay clock output from the last differential delay unit, and, A voltage control delay unit is a clock recovery circuit of a display that controls the delay time of the differential delay units according to the level of the voltage control signal.
15. In claim 14, each of the above differential delay units is, A first input circuit that delays the first input and transmits it to the first node; A second input circuit that delays and transmits a second input, which is differential to the first input, to a second node; A differential comparison circuit that compares a first output of a first input circuit applied through the first node and a second output of a second input circuit applied through the second node, and outputs a first differential delay clock and a second differential delay clock in a differential state as a result of the comparison through the first node and the second node; An inverter that outputs the delay clock obtained by inverting the first differential delay clock of the first node; and A control circuit that controls the driving current of the first input circuit and the second input circuit, respectively, in response to the above voltage control signal; is included. If the above differential delay unit is the first differential delay unit, the first input and the second input correspond to the first differential clock and the second differential clock, and, When the above differential delay unit is the above second differential delay unit, the above first input and the above second input are a clock recovery circuit of a display corresponding to the above first differential delay clock and the above second differential delay clock output from the preceding differential delay unit.
16. In claim 13, the delay compensator is, It includes a first capacitor bank and a second capacitor bank coupled to a first input side and a second input side into which the first differential clock and the second differential clock of the first differential delay unit are input, and A clock recovery circuit for a display that controls the capacitances of the first capacitor bank and the second capacitor bank in correspondence with the delay time difference so that the first delay time and the second delay time are the same.
17. In claim 13, the delay compensator is, A first time digital converter that compares the first differential clock on the input side of the first differential delay unit with the second delay clock on the output side and outputs a first delay value corresponding to the first delay time; A second time digital converter that compares the input-side third delay clock and the output-side fourth delay clock of the second differential delay unit and outputs a second delay value corresponding to the second delay time; A comparator that compares the first delay value and the second delay value and outputs a comparison value corresponding to the delay time difference; and A clock recovery circuit for a display, characterized by comprising: a first capacitor bank and a second capacitor bank coupled to a first input side and a second input side into which the first differential clock and the second differential clock of the first differential delay unit are input, and providing the capacitance controlled in correspondence with the comparison value.
18. In Article 17, The second differential delay unit of the above multi-stage delay chain is selected as the second differential delay unit, and The above second delay clock is a clock recovery circuit of the display identical to the above third delay clock.
19. In Article 17, The first time digital converter receives the first differential clock as a first start clock and the second delay clock as a first stop clock, and includes a first chain of first unit delay cells that stepwise shift the first start clock and the first stop clock; The second time digital converter receives the third delay clock as a second start clock and the fourth delay clock as a second stop clock, and includes a second chain of second unit delay cells that stepwise shift the second start clock and the second stop clock; Each of the above-mentioned first unit delay cells shifts the first start clock by delaying it further than the first stop clock by a preset unit delay difference time, and outputs a first difference value that determines the phase of the received first start clock based on the received first stop clock; Each of the above-mentioned second unit delay cells receives the third delay clock as a second start clock and receives the fourth delay clock as a second stop clock, shifts the second start clock by delaying it further than the second stop clock by the unit delay difference time, and outputs a second difference value in which the phase of the second start clock is determined based on the second stop clock; The first time digital converter outputs the first difference values as the first delay values; and, The above second time digital converter is a clock recovery circuit of a display that outputs the above second difference values as the above second delay values.
20. In Article 19, The above first unit delay cell is, A first buffer that shifts the above first stop clock by delaying it by a first unit delay time; A second buffer that shifts the first start clock by delaying it by a second unit delay time, which is the sum of the first unit delay time and the unit delay difference time; and A first phase determiner that outputs a first difference value for determining the phase of the first start clock based on the first stop clock: and, The above second unit delay cell is, A third buffer that shifts the second stop clock by delaying it by the first unit delay time; A fourth buffer that shifts the second start clock by delaying it by the second unit delay time; and A clock recovery circuit of a display comprising a second phase determiner that outputs a second difference value for determining the phase of the second start clock based on the second stop clock.

Description

Clock Recovery Circuit for Display The present invention relates to a clock recovery circuit for a display, and more specifically, to a clock recovery circuit for a display that recovers a clock from a clock data signal in which a clock is embedded. The display may include a data transmission device, a data reception device, and a display panel. The data transmission device is configured to transmit data for display. The aforementioned data transmission device can be understood as a general timing controller. For example, data may be transmitted in a format in which a clock is embedded, and the signal transmitted in this way may be referred to as a clock data signal. A data receiving device may be configured to receive a clock data signal, recover a clock from the clock data signal, recover data using the recovered clock, and generate and output a source signal for display using the recovered clock. The above-mentioned data receiving device can be understood as a general source driver. The display panel can display a desired image by receiving the above-mentioned source signal. The data receiving device needs to extract and restore the clock from the clock data signal without a separate oscillator, and to this end, it may be equipped with a clock restoration circuit. The clock recovery circuit can be designed to recover the clock without a separate oscillator by being configured based on a delay lock loop. The delay lock loop configured in the clock recovery circuit may include delay units that form a multi-stage delay chain. Generally, the time constant acting on the transmission of the clock between the delay units of a delay chain can be formed uniformly. However, the time constant acting on the input side of the first delay unit of the delay units receiving the clock extracted from the clock data signal can be formed differently from the time constant between the delay units. This phenomenon may occur because the input/output capacitance formed between the delay units differs from the capacitance on the input side of the first delay unit. The aforementioned difference in capacitance may be caused by factors such as the influence of the manufacturing process of the data receiving device. The aforementioned difference in capacitance causes a difference in delay time between the first delay unit and the remaining delay unit, and this difference in delay time affects the margin for setting up or holding data when recovering data using the recovery clock. In particular, in the case of high-speed operation where the data recovery time is short, this difference in delay time may cause difficulties in data recovery. In addition, the delay-locked loop configured in the clock recovery circuit generally forms a multi-stage delay chain using an inverter chain. That is, the delay units forming the multi-stage delay chain can be configured using inverters. As described above, when using a multi-stage delay chain with an inverter chain, the range of operating frequencies at which the clock can be controlled per delay chain is narrow. Consequently, there is a problem in that the operating frequency at which the clock can be restored is limited. FIG. 1 is a block diagram showing a preferred embodiment of a clock recovery circuit of a display. FIG. 2 is a circuit diagram showing an example of a differential delay unit. FIG. 3 is a block diagram showing an example of a delay compensator. FIG. 4 is a waveform diagram illustrating the case where the first differential delay unit has a slower delay time than the remaining differential delay units. FIG. 5 is a waveform diagram illustrating the case where the first differential delay unit has a faster delay time than the remaining differential delay units. FIG. 6 is a waveform diagram illustrating the case in which the delay time of the first differential delay unit in the case of FIG. 4 is compensated by the embodiment. FIG. 7 is a waveform diagram illustrating the case in which the delay time of the first differential delay unit in the case of FIG. 5 is compensated by the embodiment. FIG. 8 is a detailed block diagram illustrating the delivery of delay clocks to time digital converters in a voltage-controlled delay section. FIG. 9 is a detailed block diagram illustrating an embodiment of a time-to-digital converter. FIG. 10 is a timing diagram illustrating the input of a time-to-digital converter. Figure 11 is a timing diagram to explain the resolution calculation of a time-to-digital converter. FIG. 12 is a detailed block diagram illustrating an embodiment of a comparator. FIG. 13 is a detailed circuit diagram illustrating an embodiment of a capacitor bank. FIG. 14 is a graph illustrating the operating frequency range according to the present invention. An embodiment of the clock recovery circuit of the display of the present invention discloses a multi-stage delay chain configured to recover a clock using differential delay units. An embodiment of the present invention may