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KR-102963246-B1 - DISPLAY DEVICE AND INSPECTION METHOD THEREOF

KR102963246B1KR 102963246 B1KR102963246 B1KR 102963246B1KR-102963246-B1

Abstract

A display device according to one embodiment comprises connection lines, PAM data lines to which PWM data voltages are respectively applied, PWM data lines to which PWM data voltages are respectively applied, a first connection control line to which a first connection control signal is applied, a second connection control line to which a second connection control signal is applied, subpixels to which the PWM data lines and the PAM data lines are respectively connected, and a first demultiplexer that connects the connection lines to the PAM data lines or connects the connection lines to the PWM data lines according to the first connection control signal and the second connection control signal.

Inventors

  • 황정환
  • 김현준
  • 이계욱
  • 정준기
  • 전상진

Assignees

  • 삼성디스플레이 주식회사

Dates

Publication Date
20260512
Application Date
20220314
Priority Date
20211019

Claims (20)

  1. Connection wires; PWM data wires to which PWM data voltages are respectively applied; PAM data wirings to which PAM data voltages are respectively applied; A first connection control wiring to which a first connection control signal is applied; A second connection control wiring to which a second connection control signal is applied; Subpixels respectively connected to the above PWM data lines and the above PAM data lines; and A display device having a first demultiplexer that connects the connection wires to the PAM data wires or connects the connection wires to the PWM data wires, respectively, according to the first connection control signal and the second connection control signal.
  2. In Article 1, The above-mentioned first demux unit is, When a first connection control signal of a gate-on voltage is input to the first connection control wiring, the connection wirings are connected to the PAM data wirings, and A display device that connects the connection wires to the PWM data wires when a second connection control signal of a gate-on voltage is input to the second connection control wire.
  3. In Article 1, The above-mentioned first demux unit is, A first connection control transistor comprising a gate electrode connected to the first connection control wiring, a first electrode connected to the first connection wiring among the connection wirings, and a second electrode connected to the first PAM data wiring among the PAM data wirings; A second connection control transistor comprising a gate electrode connected to the first connection control wiring, a first electrode connected to the second connection wiring among the connection wirings, and a second electrode connected to the second PAM data wiring among the PAM data wirings; and A display device comprising a third connection control transistor including a gate electrode connected to the first connection control wiring, a first electrode connected to the third connection wiring among the connection wirings, and a second electrode connected to the third PAM data wiring among the PAM data wirings.
  4. In Article 1, The above-mentioned first demux unit is, A fourth connection control transistor comprising a gate electrode connected to the second connection control wire, a first electrode connected to the first connection wire among the connection wires, and a second electrode connected to the first PWM data wire among the PWM data wires; A fifth connection control transistor comprising a gate electrode connected to the second connection control wire, a first electrode connected to the second connection wire among the connection wires, and a second electrode connected to the second PWM data wire among the PWM data wires; and A display device comprising a third connection control transistor including a gate electrode connected to a third connection control wire, a first electrode connected to the third connection wire among the connection wires, and a second electrode connected to the third PWM data wire among the PWM data wires.
  5. In Article 1, Fan-out wiring to which PWM data voltages are applied; A first demultiplexer control wiring to which a first demultiplexer control signal is applied; A second demultiplexer control wiring to which a second demultiplexer control signal is applied; and Further comprising a third demultiplexer control wiring to which a third demultiplexer control signal is applied, The above-mentioned first demux unit is, A display device that selectively connects the fan-out wiring to Q (where Q is an integer greater than or equal to 2) of the connection wirings according to the first demultiplex control signal, the second demultiplex control signal, and the third demultiplex control signal.
  6. In Article 5, The above-mentioned first demux unit is, When a first demultiplexer control signal of a gate-on voltage is applied to the first demultiplexer control wiring, the fan-out wiring is connected to the first connecting wiring among the Q connecting wirings, and When a second demultiplexer control signal of a gate-on voltage is applied to the second demultiplexer control wiring, the fan-out wiring is connected to the second connecting wiring among the Q connecting wirings, and A display device that connects the fan-out wiring to the third connecting wiring among the Q connecting wirings when a third demultiplexer control signal of the gate-on voltage is applied to the third demultiplexer control wiring.
  7. In Article 5, The above-mentioned first demux unit is, A first demultiplexer transistor comprising a gate electrode connected to the first demultiplexer control wiring, a first electrode connected to the fan-out wiring, and a second electrode connected to the first connecting wiring among the connecting wirings; A second demultiplexer transistor comprising a gate electrode connected to the second demultiplexer control wiring, a first electrode connected to the fan-out wiring, and a second electrode connected to the second connecting wiring among the connecting wirings; and A display device comprising a third demultiplex transistor including a gate electrode connected to the third demultiplex control wiring, a first electrode connected to the fan-out wiring, and a second electrode connected to the third connecting wiring among the connecting wirings.
  8. In Article 1, A first PWM control wiring to which a first PWM control signal is applied; A second PWM control wiring to which a second PWM control signal is applied; A third PWM control wiring to which a third PWM control signal is applied; and A display device further comprising a second demultiplexer that connects the PWM data lines to a first power line to which a first power voltage is applied, according to the first PWM control signal, the second PWM control signal, and the third PWM control signal.
  9. In Article 8, The above second demux unit is, When a first PWM control signal of a gate-on voltage is applied to the first PWM control wiring, the first PWM data wiring among the PWM data wirings is connected to the first power wiring, and When a second PWM control signal of a gate-on voltage is applied to the second PWM control wiring, the second PWM data wiring among the PWM data wirings is connected to the first power wiring, and A display device that connects the third PWM data line among the PWM data lines to the first power line when a third PWM control signal of the gate-on voltage is applied to the third PWM control line.
  10. In Article 8, The above second demux unit is, A first PWM control transistor comprising a gate electrode connected to the first PWM control wiring, a first electrode connected to the first PWM data wiring among the PWM data wirings, and a second electrode connected to the first power wiring; A second PWM control transistor comprising a gate electrode connected to the second PWM control wiring, a first electrode connected to the second PWM data wiring among the PWM data wirings, and a second electrode connected to the first power wiring; and A display device comprising a third PWM control transistor including a gate electrode connected to the third PWM control wiring, a first electrode connected to the third PWM data wiring among the PWM data wirings, and a second electrode connected to the first power wiring.
  11. In Article 8, First PAM pad wiring to which the first PWM data voltage is applied; A second PAM pad wiring to which a second PWM data voltage is applied; and Further comprising a third PAM pad wiring to which a third PWM data voltage is applied, The above second demux unit is, A display device that, when a second connection control signal of a gate-on voltage is input to the second connection control wiring, connects the first PAM pad wiring to the first PAM data wiring among the PAM data wirings, connects the second PAM pad wiring to the second PAM data wiring among the PAM data wirings, and connects the third PAM pad wiring to the third PAM data wiring among the PAM data wirings.
  12. In Article 1, The above subpixel is, PWM light-emitting wiring to which a PWM light-emitting signal is applied; PAM light-emitting wiring to which a PAM light-emitting signal is applied; A first pixel driver that supplies a control current to a first node according to a first PWM data voltage among the PWM data voltages according to the above PWM light emission signal; A second pixel driver that generates a driving current according to a second PWM data voltage among the PWM data voltages according to the above PWM light emission signal; and A display device comprising a third pixel driver that supplies the driving current to the light-emitting element according to the above PAM light-emitting signal and the voltage of the first node.
  13. In Article 12, Scan write wiring to which a scan write signal is applied; Scan initialization wiring to which a scan initialization signal is applied; Scan control wiring to which a scan control signal is applied; PWM light-emitting wiring to which a PWM light-emitting signal is applied; PAM light-emitting wiring to which a PAM light-emitting signal is applied; Sweep signal wiring to which a sweep signal is applied; Initialization voltage wiring to which an initialization voltage is applied; and Further comprising a first power supply voltage wiring to which a first power supply voltage is applied, The above-mentioned first pixel driving unit is, A first transistor that generates the control current according to the first PWM data voltage; A second transistor that applies the first PWM data voltage of the first PWM data line among the PWM data lines to the first electrode of the first transistor according to the scan write signal; A third transistor that applies the initialization voltage of the initialization voltage wiring to the gate electrode of the first transistor according to the scan initialization signal; A fourth transistor that connects the gate electrode and the second electrode of the first transistor according to the above scan write signal; A fifth transistor that connects the first power supply voltage wiring to the first electrode of the first transistor according to the above PWM light emission signal; A sixth transistor that connects the second electrode of the first transistor to the first node according to the above PWM light emission signal; A seventh transistor that connects the sweep signal wiring to the gate off voltage wiring to which the gate off voltage is applied according to the scan control signal; and A display device comprising a first capacitor disposed between the sweep signal wiring and the gate electrode of the first transistor.
  14. In Article 12, Scan write wiring to which a scan write signal is applied; Scan initialization wiring to which a scan initialization signal is applied; Scan control wiring to which a scan control signal is applied; PWM light-emitting wiring to which a PWM light-emitting signal is applied; PAM light-emitting wiring to which a PAM light-emitting signal is applied; Sweep signal wiring to which a sweep signal is applied; Initialization voltage wiring to which the initialization voltage is applied; A first power supply voltage wiring to which a first power supply voltage is applied; and Further comprising a second power supply voltage wiring to which a second power supply voltage is applied, The above second pixel driving unit is, An eighth transistor that generates the driving current according to the second PWM data voltage; A ninth transistor that applies the second PWM data voltage of the second PWM data line among the PWM data lines to the first electrode of the eighth transistor according to the scan write signal; A 10th transistor that applies the initialization voltage of the initialization voltage wiring to the gate electrode of the 8th transistor according to the scan initialization signal; An 11th transistor connecting the gate electrode and the 2nd electrode of the 8th transistor according to the above scan write signal; A 12th transistor that connects the 1st power supply voltage wiring to the 2nd node according to the above scan control signal; A 13th transistor that connects the second power supply voltage wiring to the first electrode of the 9th transistor according to the above PWM light emission signal; A 14th transistor that connects the second power supply voltage wiring to the second node according to the above PWM light emission signal; and A display device comprising a second capacitor disposed between the gate electrode of the ninth transistor and the second node.
  15. In Article 12, Scan write wiring to which a scan write signal is applied; Scan initialization wiring to which a scan initialization signal is applied; Scan control wiring to which a scan control signal is applied; PWM light-emitting wiring to which a PWM light-emitting signal is applied; PAM light-emitting wiring to which a PAM light-emitting signal is applied; Sweep signal wiring to which a sweep signal is applied; Initialization voltage wiring to which the initialization voltage is applied; A first power supply voltage wiring to which a first power supply voltage is applied; A second power supply voltage wiring to which a second power supply voltage is applied; and Further comprising a third power supply voltage wiring to which a third power supply voltage is applied, The above third pixel driving unit is, A 15th transistor including a gate electrode connected to a 3rd node; A 16th transistor that connects the 3rd node to the initialization voltage wiring according to the scan control signal; A 17th transistor that connects the second electrode of the 15th transistor to the first electrode of the light-emitting element according to the above PAM light-emitting signal; A 18th transistor that connects the first electrode of the light-emitting element to the initialization voltage wiring according to the above scan control signal; and A display device comprising a third capacitor disposed between the third node and the initialization voltage wiring.
  16. Fan-out wiring to which PWM data voltages are applied; PAM data wirings to which PAM data voltages are respectively applied; PWM data wires to which PWM data voltages are respectively applied; Subpixels respectively connected to the above PWM data lines and the above PAM data lines; A first demultiplexer unit that controls the connection between the fan-out wiring and the PWM data wiring and the connection between the fan-out wiring and the PAM data wiring; and A display device having a second demultiplexer that controls the connection between the above PWM data lines and the first power line to which the first power voltage is applied.
  17. In Article 16, A first pad portion including a data pad connected to the above fan-out wiring; and A second pad portion including a power pad connected to the first power wiring is further provided, and The first pad portion is positioned on one side of the display panel, and The second pad portion is a display device positioned on the other side opposite to one side of the display panel.
  18. In Article 17, The first demultiplexer is positioned adjacent to the first pad portion, and The second demultiplexer is a display device positioned adjacent to the second pad.
  19. In Article 17, A first circuit board connected to the first pad portion; A source driving circuit disposed on the first circuit board and outputting the PWM data voltages; A second circuit board connected to the second pad portion; and A display device further comprising a power supply circuit disposed on the second circuit board and outputting the PWM data voltages and the first power supply voltage.
  20. Fan-out wiring to which PWM data voltages are applied; A first power wiring to which a first power voltage is applied; PAM pad wiring to which PAM data voltages are applied; PWM data wires connected to the fan-out wiring in the first mode and connected to the first power wiring in the second mode; PAM data wires each connected to the PAM pad wires in the first mode and connected to the fan-out wire in the second mode; and A display device having subpixels connected to the above PWM data lines and the above PAM data lines, respectively.

Description

Display device and inspection method thereof The present invention relates to a display device and a method for inspecting the same. As the information society develops, the demand for display devices to display images is increasing in various forms. Display devices may be flat panel display devices such as Liquid Crystal Displays, Field Emission Displays, and Light Emitting Displays. The light-emitting display device may include an organic light-emitting display device comprising an organic light-emitting diode element as a light-emitting element, or a light-emitting diode display device comprising an inorganic light-emitting diode element such as an LED (Light Emitting Diode) as a light-emitting element. Since the wavelength of light emitted by an inorganic light-emitting diode element varies depending on the driving current, when adjusting the brightness or gradation of the light of the inorganic light-emitting diode element by adjusting the magnitude of the driving current applied to the inorganic light-emitting diode element, the quality of the image may be lowered. FIG. 1 is a block diagram showing a display device according to one embodiment. FIG. 2 is a circuit diagram showing a first subpixel according to one embodiment. FIG. 3 is a graph showing the wavelength of light emitted by the light-emitting element of the first subpixel, the wavelength of light emitted by the light-emitting element of the second subpixel, and the wavelength of light emitted by the light-emitting element of the third subpixel according to the driving current according to one embodiment. FIG. 4 is a graph showing the luminous efficiency of a light-emitting element of a first subpixel, the luminous efficiency of a light-emitting element of a second subpixel, and the luminous efficiency of a light-emitting element of a third subpixel according to a driving current according to one embodiment. FIG. 5 is an example diagram showing the operation of a display device during the Nth to N+2nd frame period. Figure 6 is another example drawing showing the operation of a display device during the Nth to N+2nd frame period. FIG. 7 is a waveform diagram showing scan initialization signals, scan write signals, scan control signals, PWM light emission signals, PAM light emission signals, and sweep signals applied to subpixels placed on the k to k+5 row lines during the Nth frame period according to one embodiment. FIG. 8 is a waveform diagram showing the period during which a k-th scan initialization signal, a k-th scan write signal, a k-th scan control signal, a k-th PWM light emission signal, a k-th PAM light emission signal, and a k-th sweep signal are applied to each of the subpixels placed on the k-th row line during the N-th frame period according to one embodiment, the voltage of the third node, and a driving current applied to the light-emitting element are applied. FIG. 9 is a timing diagram showing the k-th sweep signal, the voltage of the gate electrode of the first transistor, the turn-on timing of the first transistor, and the turn-on timing of the 15th transistor during the fifth and sixth periods according to one embodiment. FIGS. 10 to 13 are circuit diagrams showing the operation of the first subpixel during the first period, second period, third period, and sixth period of FIG. 8. FIG. 14 is an example drawing showing a display device according to one embodiment. FIG. 15 is a circuit diagram showing a first demultiplexer section according to one embodiment. FIG. 16 is a circuit diagram showing a second demultiplexer section according to one embodiment. FIG. 17 is a waveform diagram showing first to third demultiplex control signals, first to third PWM control signals, first connection control signal, and second connection control signal input to the first demultiplex unit and the second demultiplex unit in the first mode. FIG. 18 is a waveform diagram showing first to third demultiplex control signals, first to third PWM control signals, first connection control signal, and second connection control signal input to the first demultiplex unit and the second demultiplex unit in the second mode. FIG. 19 is a flowchart showing a method for inspecting a display device according to one embodiment. FIG. 20 is a circuit diagram showing a first subpixel according to another embodiment. FIG. 21 is a waveform diagram showing the period during which a k-th scan initialization signal, a k-th scan write signal, a k-th scan control signal, a k-th PWM light emission signal, a k-th PAM light emission signal, and a k-th sweep signal are applied to each of the subpixels placed on the k-th row line during the N-th frame period according to another embodiment, the voltage of the third node, and a driving current applied to the light-emitting element are applied. FIGS. 22 to 24 are circuit diagrams showing the operation of the first subpixel during the first period, the second period, and the fifth period of FIG. 21. FIG. 25 is a circuit diagra