KR-102963255-B1 - Low-noise quadrature phase signal generation

Abstract

An orthogonal phase clock generator is disclosed. The orthogonal phase clock generator may include a first injection synchronous oscillator, a phase interpolator, and a second injection synchronous oscillator. The first injection synchronous oscillator may generate a first plurality of clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection synchronous oscillator may generate a second plurality of clock signals from the second reference clock signal. The first orthogonal phase clock signal may be selected from the first plurality of clock signals, and the second orthogonal phase clock signal may be selected from the second plurality of reference clock signals.

Inventors

• 신, 재욱
• 우파드햐야, 파라그
• 마, 샤오준

Assignees

• 자일링크스 인코포레이티드

Dates

Publication Date

20260508

Application Date

20200817

Priority Date

20191119

Claims (15)

1. As a quadrature clock generator, A first injection-locked oscillator configured to generate a plurality of first clock signals based at least partially on a first reference clock signal; A first selection circuit coupled to the first injection synchronous oscillator and configured to select one of the first clock signals as a transmit quadrature phase clock signal — the transmit quadrature phase clock signal is provided to a transmit circuit —; A phase interpolator coupled to the first injection synchronous oscillator and configured to generate a second reference clock signal based on a selected pair of first clock signals; A second injection synchronous oscillator configured to generate a plurality of second clock signals based at least partially on the second reference clock signal; and A second selection circuit coupled to the second injection synchronous oscillator and configured to select one of the second clock signals as a received quadrature phase clock signal — the received quadrature phase clock signal is provided to a receiving circuit — An orthogonal phase clock generator including
2. In paragraph 1, An quadrature clock generator, wherein the transmitted quadrature clock signal comprises a first in-phase (I) component and a first quadrature (Q) component, and the received quadrature clock signal comprises a second I component and a second Q component.
3. In paragraph 1, An orthogonal phase clock generator, wherein the transmitting circuit is an associated programmable device and the receiving circuit is of the associated programmable device.
4. In paragraph 3, The above phase interpolator is an orthogonal phase clock generator configured to generate the second reference clock signal based at least partially on the input signal provided by the receiving circuit.
5. In paragraph 1, An orthogonal phase clock generator in which each of the plurality of first clock signals is offset in phase from each other by 45 degrees, and each of the plurality of second clock signals is offset in phase from each other by 45 degrees.
6. In paragraph 1, The first injection synchronous oscillator, the phase interpolator, and the second injection synchronous oscillator are quadrature phase clock generators controlled at least partially by a reference voltage.
7. In paragraph 6, A quadrature-locked loop (QLL) configured to generate a control signal based at least partially on the plurality of second clock signals; and A voltage regulator configured to generate the reference voltage based at least partially on the control signal. An orthogonal phase clock generator including further
8. In Paragraph 7, An quadrature phase clock generator further comprising a coarse frequency tracking circuit configured to selectively disable the control signal based at least partially on detecting a start-up condition.
9. In paragraph 1, The first injection synchronous oscillator is at least partially controlled by a first reference voltage, and The above phase interpolator and the above second injection synchronous oscillator are quadrature phase clock generators controlled at least partially by a second reference voltage.
10. In Paragraph 9, A first QLL (quadrature-locked loop) configured to generate a first control signal based at least partially on the plurality of first clock signals; A first voltage regulator configured to generate the first reference voltage based at least partially on the first control signal; A second QLL configured to generate a second control signal based at least partially on the plurality of second clock signals; and A second voltage regulator configured to generate the second reference voltage based at least partially on the second control signal. An orthogonal phase clock generator including further
11. In Paragraph 10, An orthogonal phase clock generator further comprising a schematic frequency tracking circuit configured to selectively disable the first control signal and the second control signal based at least partially on detecting a starting condition.
12. As a programmable logic device, A transmission data processing block configured to transmit data using a transmission quadrature phase clock signal; A receiving data processing block configured to receive data using a receiving quadrature phase clock signal; and An orthogonal phase clock generator coupled to the transmission data processing block and the reception data processing block Includes, and the orthogonal phase clock generator, A first injection synchronous oscillator configured to generate a plurality of first clock signals based at least partially on a first reference clock signal; A first selection circuit configured to select one of the first clock signals as the transmission quadrature phase clock signal; A phase interpolator coupled to the first injection synchronous oscillator and configured to generate a second reference clock signal based on a selected pair of first clock signals; A second injection synchronous oscillator configured to generate a plurality of second clock signals based at least partially on a second reference clock signal; A second selection circuit configured to select one of the second clock signals as the received quadrature phase clock signal. A programmable logic device including
13. In Paragraph 12, A programmable logic device in which the first injection synchronous oscillator, the phase interpolator, and the second injection synchronous oscillator are at least partially controlled by a reference voltage.
14. In Paragraph 13, A quadrature-locked loop (QLL) configured to generate a control signal based at least partially on the plurality of second clock signals; and A voltage regulator configured to generate the reference voltage based at least partially on the control signal. A programmable logic device that further includes
15. As a method for operating an orthogonal phase clock generator, A step of generating a plurality of first clock signals based at least partially on a first reference clock signal; A step of selecting one of the plurality of first clock signals as a transmission quadrature phase clock signal — the transmission quadrature phase clock signal is provided to a transmission circuit —; A step of generating a second reference clock signal based at least partially on the plurality of first clock signals; A step of generating a plurality of second clock signals based at least partially on the second reference clock signal; and A step of selecting one of the plurality of second clock signals as a receiving quadrature phase clock signal — the receiving quadrature phase clock signal is provided to a receiving circuit — A method for operating an orthogonal phase clock generator including

Description

Low-noise quadrature phase signal generation The aspects of the present disclosure generally relate to oscillators, and more specifically to oscillators configured to generate quadrature clock signals. Many wireless and wired communication systems utilize Quadrature Amplitude Modulation (QAM) transceivers to transmit and receive data. Many QAM transceivers include quadrature clock signal generators to provide in-phase (I) and quadrature (Q) clock signals used to modulate or encode transmitted data and to demodulate or decode received data. Phase mismatch between the I and Q clock signals can induce I/Q mismatch faults in transmitted and received signals, which can ultimately lead to signal degradation and data errors. Since I/Q phase mismatch can be related to clock frequencies, minimizing I/Q phase mismatch is becoming increasingly important as clock frequencies increase, for example, in multi-gigabit SERial/DESerial-based communications. The content of the present invention is provided to introduce, in a simplified form, various concepts that are further described in the specific details for carrying out the invention below. The content of the present invention is not intended to identify core or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Furthermore, each of the systems, methods, and devices of the present disclosure has several innovative aspects, and no single aspect of these aspects alone possesses the preferred attributes disclosed herein. One innovative aspect of the claimed subject matter described in this disclosure can be used to reduce phase mismatch between in-phase (I) clock and quadrature phase (Q) clock signals in quadrature phase clock generators. In some embodiments, the quadrature phase clock generator may include a first injection-locked oscillator, a configured second injection-locked oscillator, a first selection circuit, a second selection circuit, and a phase interpolator. The first injection-locked oscillator may be configured to generate a plurality of first clock signals based at least partially on a first reference clock signal. The first selection circuit may be coupled to the first injection-locked oscillator and may be configured to select one of the first clock signals as a transmitted quadrature phase clock signal. The phase interpolator may be coupled to the first injection-locked oscillator and may be configured to generate a second reference clock signal based on a plurality of first clock signals. The second injection synchronous oscillator may be configured to generate a plurality of second clock signals based at least partially on the second reference clock signal. A second selection circuit is coupled to the second injection synchronous oscillator and configured to select one of the second clock signals as a received quadrature phase clock signal. Other innovative aspects of the claimed subject matter described in this disclosure may be implemented in a programmable logic device. In some implementations, the programmable logic device may include a transmit data processing block, a receive data processing block, and an quadrature phase clock generator. The transmit data processing block may be configured to transmit data using a transmit quadrature phase signal, and the receive data processing block may be configured to receive data using a receive quadrature phase signal. The quadrature phase clock generator may be coupled to the transmit data processing block and the receive data processing block, and may include a first injection synchronous oscillator, a first selection circuit, a phase interpolator, a second injection synchronous oscillator, and a second selection circuit. The first injection synchronous oscillator may be configured to generate a plurality of first clock signals based at least partially on a first reference clock signal. The first selection circuit may be configured to select one of the first clock signals as a transmit quadrature phase clock signal. A phase interpolator may be coupled to a first injection synchronous oscillator and configured to generate a second reference clock signal based on a selected pair of first clock signals. The second injection synchronous oscillator may be configured to generate a plurality of second clock signals based at least partially on the second reference clock signal. A second selection circuit may be configured to select one of the second clock signals as a received quadrature phase clock signal. Another innovative aspect of the claimed subject matter described in the present disclosure may be implemented as a method for operating an orthogonal phase clock generator. In some implementations, the method may include: generating a plurality of first clock signals based at least partially on a first reference clock signal; selecting one of the plurality of first clock signals as a transmitted orthogonal phase clock signal; generating a sec