KR-102963331-B1 - MULTILAYER CERAMIC ELECTRONIC COMPONENT

KR102963331B1KR 102963331 B1KR102963331 B1KR 102963331B1KR-102963331-B1

Abstract

Providing a multilayer ceramic electronic component capable of improving moisture resistance while suppressing crack formation in the laminate. The cross-sectional lower electrode layer (501) has a lower electrode layer (51) with a high porosity and an upper electrode layer (52) positioned on the outer surface side of the lower electrode layer (51) and having a lower porosity than the lower electrode layer (51). The first degree of irregularity, which is the ratio (LA2/LA1) of the length (LA2) along the outer surface side profile line (511) of the upper electrode layer (52) to the length (LA1) of the first reference line (511A) smoothed by fitting the outer surface side profile line (511) of the upper electrode layer (52), is smaller than the second degree of irregularity, which is the ratio (LB2/LB1) of the length (LB2) along the laminated side profile line (510) of the lower electrode layer (51) to the length (LB1) of the second reference line fitted in a straight line of the cross-section (LS).

Inventors

시오타 카즈나리

Assignees

가부시키가이샤 무라타 세이사쿠쇼

Dates

Publication Date: 20260511
Application Date: 20250107
Priority Date: 20240327

Claims (4)

A laminated body comprising a plurality of stacked ceramic layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing in the height direction, a first side surface and a second side surface facing in the width direction orthogonal to the height direction, and a first end surface and a second end surface facing in the length direction orthogonal to the height direction and the width direction, A first external electrode disposed on the first cross-section above, and A multilayer ceramic electronic component having a second external electrode disposed on the second cross-section, The above first external electrode is It has a first cross-sectional side external electrode disposed on the first cross-section, and The above second external electrode is It has a second cross-sectional side external electrode disposed on the second cross-section above, and The first cross-sectional side external electrode and the second cross-sectional side external electrode each have a cross-sectional side lower electrode layer and a cross-sectional side plating layer disposed on the outer surface side rather than the cross-sectional side lower electrode layer. The above-mentioned cross-sectional lower electrode layer has a lower lower electrode layer disposed on the laminated side and having a high porosity, and an upper lower electrode layer disposed on the outer surface side rather than the lower lower electrode layer and having a lower porosity than the porosity of the lower lower electrode layer. In the cross-section plane in a plane parallel to the longitudinal and height directions, A multilayer ceramic electronic component, wherein the first degree of irregularity, which is the ratio of the length measured along the outer surface side profile line of the upper layer lower electrode layer to the length of the first reference line smoothed by fitting the outer surface side profile line of the upper layer lower electrode layer, is smaller than the second degree of irregularity, which is the ratio of the length measured along the laminate side profile line of the lower layer lower electrode layer to the length of the second reference line fitted in a straight line to the cross-section of the laminate.
In paragraph 1, The above first cross-sectional side external electrode and the above second cross-sectional side external electrode are It further has a cross-sectional conductive resin layer disposed on the upper lower electrode layer above, and A multilayer ceramic electronic component in which the above-mentioned cross-sectional plating layer is disposed on the above-mentioned cross-sectional conductive resin layer.
In paragraph 1 or 2, The porosity of the lower electrode layer is 20% or more and 50% or less, and A multilayer ceramic electronic component in which the porosity of the upper and lower electrode layers is less than 20%.
In paragraph 1 or 2, A multilayer ceramic electronic component in which the ratio of the first degree of irregularity to the second degree of irregularity is 0.75 or less.

Description

Multilayer Ceramic Electronic Components The present invention relates to a multilayer ceramic electronic component. Recently, multilayer ceramic capacitors as multilayer ceramic electronic components are required to have durability under harsh environments, such as bending stress caused by thermal expansion, and in response to this, a technology using a thermosetting conductive resin paste on the external electrode of a multilayer ceramic capacitor is known. Patent Document 1 can be cited as an example of this type of technology. Patent Document 1 describes a multilayer ceramic capacitor having an external electrode having a layer composition in which an electrode layer coated by dipping and baking a conductive paste, a conductive epoxy-based thermosetting resin layer, a nickel plating layer, and a tin layer are sequentially stacked. FIG. 1 is an external perspective view of a multilayer ceramic capacitor of the present embodiment. Figure 2 is a cross-sectional view along line II-II of the multilayer ceramic capacitor shown in Figure 1. Figure 3 is a cross-sectional view along line III-III of the multilayer ceramic capacitor shown in Figure 2. Figure 4 is a cross-sectional view along line IV-IV of the multilayer ceramic capacitor shown in Figure 2. Figure 5 is an enlarged view of the V portion of the multilayer ceramic capacitor shown in Figure 2, and is a schematic diagram for explaining the porosity and the degree of surface irregularity of the lower electrode layer on the cross-sectional side of the multilayer ceramic capacitor. Figure 6 is a schematic diagram showing an example of the configuration of a double-layered ceramic capacitor. Figure 7 is a schematic diagram showing an example of the configuration of a triple-layer ceramic capacitor. FIG. 8 is a schematic diagram showing an example of the configuration of a 4-row multilayer ceramic capacitor. <Embodiment> Hereinafter, a multilayer ceramic capacitor (1) as a multilayer ceramic electronic component according to the first embodiment of the present disclosure will be described using FIGS. 1 to 4. FIG. 1 is an external perspective view of the multilayer ceramic capacitor (1) of the present embodiment. FIG. 2 is a cross-sectional view along line II-II of the multilayer ceramic capacitor (1) of FIG. 1. FIG. 3 is a cross-sectional view along line III-III of the multilayer ceramic capacitor (1) of FIG. 2. FIG. 4 is a cross-sectional view along line IV-IV of the multilayer ceramic capacitor (1) of FIG. 2. Meanwhile, drawings may be schematically simplified to explain the content of the invention, and the ratio of dimensions of the depicted components or between components may not match the ratio of their dimensions described in the specification. Additionally, there may be cases where components described in the specification are omitted from the drawings, or where the number is omitted. For example, the number of internal electrode layers described in FIGS. 2 and FIGS. 3 is 10 layers for convenience of explanation, but this does not represent the actual number of internal electrode layers (30). Meanwhile, regarding the shapes or geometric conditions used in the present invention and terms specifying their degree, such as "parallel," "orthogonal," "identical," and values of length or angle, they are not bound by their strict meanings and are interpreted to include a range that allows for the expectation of similar functions. A multilayer ceramic capacitor (1) has a laminate (10) and an external electrode (40). FIGS. 1 to 4 illustrate an XYZ orthogonal coordinate system. The length direction (L) of the multilayer ceramic capacitor (1) and the laminate (10) corresponds to the X direction. The width direction (W) of the multilayer ceramic capacitor (1) and the laminate (10) corresponds to the Y direction. The stacking direction (T) as the height direction of the multilayer ceramic capacitor (1) and the laminate (10) corresponds to the Z direction. Here, the cross-section shown in FIG. 2 is also referred to as the LT cross-section. The cross-section shown in FIG. 3 is also referred to as the WT cross-section. The cross-section shown in FIG. 4 is also referred to as the LW cross-section. As shown in FIGS. 1 to 4, the laminate (10) includes a first main surface (TS1) and a second main surface (TS2) facing in the stacking direction (T), a first side surface (WS1) and a second side surface (WS2) facing in the width direction (W) orthogonal to the stacking direction (T), and a first cross section (LS1) and a second cross section (LS2) facing in the length direction (L) orthogonal to the stacking direction (T) and the width direction (W). As shown in FIG. 1, the laminate (10) has a roughly rectangular shape. Meanwhile, the length (L) dimension of the laminate (10) is not necessarily longer than the width (W) dimension. It is preferable that the corners and ridges of the laminate (10) be rounded. The corners are the parts where three sides of the laminate (10) in