KR-102963341-B1 - MULTI BRIDGE CHANNEL FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME

Abstract

A multi-bridge channel field-effect transistor comprises a substrate, a first source/drain pattern provided on the substrate, a second source/drain pattern spaced apart from the first source/drain pattern along a first direction on the substrate, a first channel layer and a second channel layer provided between the first source/drain pattern and the second source/drain pattern, a first graphene barrier provided between the first channel layer and the first source/drain pattern, a gate insulating film surrounding the first channel layer, and a gate electrode surrounding the first channel layer with the gate insulating film in between.

Inventors

• 김창현
• 김언기
• 정아름
• 변경은

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20210910

Claims (20)

1. Substrate; A first source/drain pattern provided on the substrate; A second source/drain pattern spaced apart along a first direction from the first source/drain pattern on the substrate; A first channel layer and a second channel layer provided between the first source/drain pattern and the second source/drain pattern; A first graphene barrier provided between the first channel layer and the first source/drain pattern; A gate insulating film surrounding the first channel layer; and A gate electrode surrounding the first channel layer with the gate insulating film in between; comprising A multi-bridge channel field-effect transistor in which the material of the first channel layer and the second channel layer is different from the material of the first graphene barrier.
2. In Article 1, The first graphene barrier is a multi-bridge channel field-effect transistor extending into the region between the second channel layer and the first source/drain pattern.
3. In Article 1, A multi-bridge channel field-effect transistor further comprising: a second graphene barrier provided between the first channel layer and the second source/drain pattern.
4. In Paragraph 3, The second graphene barrier is a multi-bridge channel field-effect transistor that extends into the region between the second channel layer and the second source/drain pattern.
5. In Article 4, The gate insulating film is a multi-bridge channel field-effect transistor extending along the surface of the first graphene barrier, the surface of the second graphene barrier, the surface of the first channel layer, and the surface of the second channel layer.
6. In Paragraph 3, Both ends along the first direction of the first channel layer are multi-bridge channel field-effect transistors that are in direct contact with the first graphene barrier and the second graphene barrier, respectively.
7. In Article 1, The first source/drain pattern and the second source/drain pattern are multi-bridge channel field-effect transistors comprising silicon germanium (SiGe).
8. In Article 1, The first source/drain pattern and the second source/drain pattern are multi-bridge channel field-effect transistors including an epitaxial layer.
9. In Article 1, A multi-bridge channel field-effect transistor in which the first channel layer and the second channel layer are arranged along a direction perpendicular to the upper surface of the substrate.
10. In Article 1, A multi-bridge channel field-effect transistor in which the thickness of the first graphene barrier is 2 nanometers (nm) or less.
11. In Article 1, The first graphene barrier above is a multi-bridge channel field-effect transistor comprising nanocrystalline graphene.
12. Forming a stacked structure comprising a plurality of support layers and a plurality of channel layers alternately stacked on a substrate; Forming a first graphene barrier on one side of the above-mentioned stacked structure; Forming a first source/drain pattern on the opposite side of the stacked structure with respect to the first graphene barrier; Selectively removing the plurality of support layers to expose the plurality of channel layers; Forming a gate insulating film on the surface of the plurality of channel layers; and Forming a gate electrode on the surface of the gate insulating film; comprising, A method for manufacturing a multi-bridge channel field-effect transistor, wherein the material of the plurality of channel layers is different from the material of the first graphene barrier.
13. In Article 12, The above plurality of support layers are selectively removed by a wet etching process using an etching solution or a dry etching process using an etching gas, and A method for manufacturing a multi-bridge channel field-effect transistor in which the first graphene barrier prevents the etching liquid or the etching gas from contacting the first source/drain pattern during a process of selectively removing the plurality of support layers.
14. In Article 12, Forming a second graphene barrier on the other side of the above-mentioned stacked structure; and Further comprising forming a second source/drain pattern on the opposite side of the stacked structure with respect to the second graphene barrier, wherein A method for manufacturing a multi-bridge channel field-effect transistor in which the second graphene barrier prevents an etching solution or etching gas that removes the plurality of support layers from contacting the second source/drain pattern during a process of selectively removing the plurality of support layers.
15. In Article 12, A method for manufacturing a multi-bridge channel field-effect transistor, further comprising: during the process of forming the gate insulating film, the gate insulating film is formed on the surface of the first graphene barrier.
16. In Article 12, A method for manufacturing a multi-bridge channel field-effect transistor in which the first graphene barrier is formed by performing a chemical vapor deposition process or an atomic layer deposition process.
17. In Article 12, A method for manufacturing a multi-bridge channel field-effect transistor in which the first source/drain pattern and the plurality of channel layers are separated from each other by the first graphene barrier.
18. In Article 12, A method for manufacturing a multi-bridge channel field-effect transistor in which the first source/drain pattern and the plurality of support layers comprise silicon germanium (SiGe).
19. In Article 12, A method for manufacturing a multi-bridge channel field-effect transistor, comprising forming the first source/drain pattern by performing an epitaxial growth process.
20. In Article 12, A method for manufacturing a multi-bridge channel field-effect transistor comprising nanocrystalline graphene, wherein the first graphene barrier above is a first graphene barrier.

Description

Multi-bridge channel field-effect transistor and method of fabricating the same The present disclosure relates to a multi-bridge channel field-effect transistor and a method for manufacturing the same. Transistors are semiconductor devices that perform the role of electrical switching and are employed in various integrated circuits, including memory, driver ICs, and logic devices. As the integration density of integrated circuits increases, the space occupied by transistors is rapidly shrinking; therefore, research is underway to maintain performance while reducing the size of transistors. It is known that as the size of transistors decreases and the channel length shortens, problems caused by the short channel effect are triggered. Examples include phenomena such as threshold voltage variation, carrier velocity saturation, and deterioration of the subthreshold characteristics. Accordingly, methods to overcome the short channel effect and effectively reduce the channel length are being sought. For example, gate all-around structures with multi-bridge channels are being developed to improve current density. However, various process problems are occurring in the fabrication of new device structures. FIG. 1 is a perspective view of a multi-bridge channel field-effect transistor according to an exemplary embodiment. Figure 2 is a cross-sectional view along line A-A' of the multi-bridge channel field-effect transistor of Figure 1. Figure 3 is a cross-sectional view along the BB' line of the multi-bridge channel field-effect transistor of Figure 1. FIGS. 4 to 8 are cross-sectional views corresponding to line A-A' of FIG. 1 to explain a method for manufacturing a multi-bridge channel field-effect transistor of FIG. 1. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of explanation. Meanwhile, the embodiments described below are merely illustrative, and various modifications are possible from these embodiments. In the following, what is described as "above" may include not only what is directly above in contact, but also what is above without contact. A singular expression includes a plural expression unless the context clearly indicates otherwise. Furthermore, when a part is said to "include" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. In addition, terms such as “...part” described in the specification refer to a unit that processes at least one function or operation. In the following, 'at least one of a, b, and c' should be understood to include 'only a', 'only b', 'only c', 'a and b', 'a and c', 'b and c', or 'a, b, and c'. FIG. 1 is a perspective view of a multi-bridge channel field-effect transistor according to an exemplary embodiment. FIG. 2 is a cross-sectional view along line A-A' of the multi-bridge channel field-effect transistor of FIG. 1. FIG. 3 is a cross-sectional view along line B-B' of the multi-bridge channel field-effect transistor of FIG. 1. Referring to FIGS. 1 to 3, a multi-bridge channel field-effect transistor (100) may be provided. The multi-bridge channel field-effect transistor (100) may include a substrate (110), a first channel layer (121), a second channel layer (122), a gate insulating film (140), a gate electrode (160), a source region (180), a drain pattern (190), a first graphene barrier (GB1), and a second graphene barrier (GB2). The substrate (110) may be an insulating substrate or a semiconductor substrate having an insulating layer formed on its surface. The insulating substrate may be, for example, a glass substrate or a sapphire substrate. The semiconductor substrate may include, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), or a III-V group semiconductor material. The substrate (110) may be, for example, a silicon substrate having silicon oxide formed on its surface, but is not limited thereto. The substrate (110) may extend along a first direction (DR1) and a second direction (DR2). A first source/drain pattern (180) and a second source/drain pattern (190) may be provided on a substrate (110). The second source/drain pattern (190) may be spaced apart from the first source/drain pattern (180) along a first direction. In one example, the first source/drain pattern (180) may be the source of a transistor device, and the second source/drain pattern (190) may be the drain of a transistor device. The first source/drain pattern (180) and the second source/drain pattern (190) may include silicon germanium (SiGe). For example, the first source/drain pattern (180) and the second source/drain pattern (190) may include a silicon germanium (SiGe) epi layer formed by an epitaxial growth process. A first channel la