KR-102963478-B1 - Semiconductor device, chip and method of manufacturing the same, memory system

Abstract

The present disclosure provides a semiconductor device, a chip, a method for manufacturing the same, and a memory system. The semiconductor device comprises a plurality of cutting lanes, a plurality of dies, and a die test structure, wherein the plurality of dies are defined by the intersection of the plurality of cutting lanes. The plurality of cutting lanes includes at least one first cutting lane, a plurality of second cutting lanes, and a third cutting lane, wherein the first cutting lane and the second cutting lane are arranged parallel to each other, and the third cutting lane is arranged intersecting the first cutting lane and the second cutting lane.

Inventors

• 모 핑
• 천 펑
• 시에 웨이
• 팡 홍
• 리우 레이
• 시아 즈리앙

Assignees

• 양쯔 메모리 테크놀로지스 씨오., 엘티디.

Dates

Publication Date

20260512

Application Date

20230807

Claims (20)

1. In semiconductor devices, A plurality of cutting lanes - the plurality of cutting lanes include at least one first cutting lane, a plurality of second cutting lanes arranged parallel to the first cutting lane, and a third cutting lane arranged intersecting the first cutting lane and the second cutting lanes -; A plurality of dies defined by the intersection of the plurality of cutting lanes; and It includes a die test structure located only in the first cutting lane, and Any one of the above at least one first cutting lane is positioned adjacent to at least one of the plurality of second cutting lanes, and At least two of the plurality of second cutting lanes are semiconductor devices positioned between two adjacent first cutting lanes.
2. In paragraph 1, A semiconductor device in which at least three of the plurality of second cutting lanes are positioned between two adjacent first cutting lanes.
3. In paragraph 1, A semiconductor device in which the number of the plurality of second cutting lanes disposed within the gap between two adjacent first cutting lanes is the same.
4. In paragraph 1, One of the above-mentioned plurality of cutting lanes includes a first dielectric layer and a second dielectric layer that are alternately stacked, and The above die test structure penetrates the plurality of cutting lanes in the stacking direction, and The above die test structure is a semiconductor device comprising a third dielectric layer and a conductive layer alternately stacked in the stacking direction.
5. In paragraph 4, A semiconductor device in which the thickness of the above die test structure is less than or equal to the thickness of the above cutting lane.
6. In paragraph 5, The die test structure includes multiple die test structures, and A semiconductor device in which die test structures having the same thickness are located in the same first cutting lane.
7. In paragraph 4, semiconductor layer; and The stack on the semiconductor layer further comprises—the stack includes the third dielectric layer and the conductive layer alternately stacked in the stacking direction—and The plurality of cutting lanes and the die test structure are semiconductor devices located on the semiconductor layer.
8. In paragraph 1, One of the plurality of dies comprises a memory device and a peripheral circuit bonded together, and the die test structure is configured for testing the electrical performance of the memory device, the peripheral circuit, or the bonding interface between the memory device and the peripheral circuit.
9. In paragraph 1, The plurality of cutting lanes and the plurality of dies form a repeating unit, and The above-mentioned repeating unit includes at least one of the first cutting lanes, and The semiconductor device described above is a semiconductor device comprising a plurality of the above-mentioned repeating units.
10. In a chip manufactured from a semiconductor device described in any one of claims 1 to 9, Stack - The above stack is Multiple conductive layers and dielectric layers arranged alternately, and Includes multiple channel structures -; A first cutting plane located at the outer edge of the stack; and It includes a second cutting surface located outside the first cutting surface, The above second cutting surface is a chip having a height smaller than the height of the above first cutting surface.
11. In a method for manufacturing a chip, A semiconductor device having a plurality of cutting lanes; wherein the plurality of cutting lanes includes at least one first cutting lane, a plurality of second cutting lanes and a third cutting lane, wherein the at least one first cutting lane and the plurality of second cutting lanes are arranged parallel to each other, at least two of the plurality of second cutting lanes are arranged between two adjacent of the at least one first cutting lane, and the third cutting lane is arranged intersecting the at least one first cutting lane and the plurality of second cutting lanes, and a die test structure is arranged on the first cutting lane; and A method for manufacturing a chip comprising cutting the semiconductor device into a plurality of chips along at least one first cutting lane, a plurality of second cutting lanes, and a third cutting lane.
12. In Paragraph 11, Cutting the semiconductor device into a plurality of chips along the at least one first cutting lane, the plurality of second cutting lanes, and the third cutting lanes is A method for manufacturing a chip comprising cutting the semiconductor device twice using two different cutting processes.
13. In Paragraph 12, Cutting the semiconductor device into a plurality of chips along the at least one first cutting lane, the plurality of second cutting lanes, and the third cutting lanes is, Forming a first groove in the first cutting lane with a first laser to remove a part of the above die test structure - the depth of the first groove is smaller than the thickness of the first cutting lane -; and A method for manufacturing a chip comprising mechanically cutting the plurality of second cutting lanes, the third cutting lanes, and the at least one first cutting lane below the first groove to form a plurality of chips.
14. In Paragraph 13, Before cutting the at least one first cutting lane, the plurality of second cutting lanes, and the third cutting lane below the first groove with a blade, the method of manufacturing the chip is, Forming a second groove in the plurality of second cutting lanes and forming a third groove in the third cutting lane using a second laser - wherein the depth of the second groove is smaller than the thickness of the plurality of second cutting lanes, and the depth of the third groove is smaller than the thickness of the third cutting lane - A method for manufacturing a chip comprising mechanically cutting the plurality of second cutting lanes, the third cutting lanes, and the at least one first cutting lane below the first groove, and cutting the at least one first cutting lane below the first groove, the plurality of second cutting lanes below the second groove, and the third cutting lane below the third groove with a blade.
15. In Paragraph 14, A method for manufacturing a chip in which the energy of the second laser is smaller than the energy of the first laser.
16. In Paragraph 11, The above semiconductor device is, A plurality of dies defined by the intersection of the plurality of cutting lanes; and It includes a die test structure located only in the first cutting lane, and A method for manufacturing a chip in which at least one of the above-mentioned first cutting lanes is disposed adjacent to at least one of the above-mentioned plurality of second cutting lanes.
17. In Paragraph 16, One of the above-mentioned plurality of cutting lanes includes a first dielectric layer and a second dielectric layer that are alternately stacked, and The above die test structure penetrates the plurality of cutting lanes in the stacking direction, and The above die test structure is a method for manufacturing a chip comprising a third dielectric layer and a conductive layer alternately stacked in the stacking direction.
18. In Paragraph 17, A method for manufacturing a chip in which the thickness of the above die test structure is smaller than or equal to the thickness of the above cutting lane.
19. In Paragraph 11, A method for manufacturing a chip in which at least three of the plurality of second cutting lanes are disposed between two adjacent first cutting lanes.
20. In Paragraph 11, The number of the plurality of second cutting lanes arranged in the gap between two adjacent first cutting lanes is the same as the number of the manufacturing method of the same chip.

Description

Semiconductor device, chip and method of manufacturing the same, memory system The present disclosure generally relates to electronic devices, and more specifically to semiconductor devices, chips, methods for manufacturing the same, and memory systems. NAND memory devices are non-volatile memory products with low power consumption, lightweight design, and excellent performance, and are widely applied in electronic products. Planar NAND devices have virtually reached the limits of scalability. To further increase memory capacity and reduce the memory cost per bit, 3D NAND memory has been proposed. In a 3D NAND memory architecture, memory cells are arranged in multiple levels stacked vertically to achieve a stacked memory architecture. As the number of stacked layers increases, the cutting process of cutting the lanes has an increasingly greater impact on the strength of the device. The present disclosure aims to provide a semiconductor device and a method for manufacturing the same for reducing the impact on the strength of the device by cutting cutting lanes. In a first embodiment, the present disclosure provides a semiconductor device comprising: a plurality of cutting lanes including at least one first cutting lane, a plurality of second cutting lanes and a third cutting lane—the first cutting lane and the second cutting lanes are arranged parallel to each other, and the third cutting lane is arranged intersecting the first cutting lane and the second cutting lane—; a plurality of dies defined by the intersection of the plurality of cutting lanes; and a die test structure located only on the first cutting lane, wherein any one of the first cutting lanes is arranged adjacent to at least one of the second cutting lanes. In some embodiments, at least three second cutting lanes are positioned between two adjacent first cutting lanes. In some embodiments, the number of second cutting lanes placed in the gap between two adjacent first cutting lanes is the same. In some embodiments, the cutting lane includes first dielectric layers and second dielectric layers that are alternately stacked, and the die test structure penetrates the cutting lane in the stacking direction of the cutting lane and includes third dielectric layers and conductive layers that are alternately stacked in the stacking direction. In some embodiments, the thickness of the die test structure is less than or equal to the thickness of the cutting lane. In some embodiments, die test structures having the same thickness are located in the same first cutting lane. In some embodiments, the semiconductor device comprises a semiconductor layer; a stack on the semiconductor layer - the stack includes a third dielectric layer and a conductive layer alternately stacked in the stacking direction -; and a cutting lane and a die test structure are located on the semiconductor layer. In some embodiments, the die includes a memory device and a peripheral circuit bonded together, and the die test structure is configured to test the electrical performance of the memory device, the peripheral circuit, or the bonding interface between the memory device and the peripheral circuit. In some embodiments, a plurality of cutting lanes and a plurality of dies constitute a repeating unit, the repeating unit includes at least one first cutting lane, and the semiconductor device includes a plurality of repeating units. In a second aspect, the present disclosure provides a chip manufactured from a semiconductor device in any one of the embodiments described above, wherein the chip comprises a first cutting surface and a second cutting surface outside the first cutting surface, and the second cutting surface has a height smaller than the height of the first cutting surface. In a third aspect, the present disclosure provides a memory system comprising: a chip provided in the above-described embodiment; and a controller electrically connected to the chip to control the chip to store data. In a fourth aspect, the present disclosure provides a semiconductor device having a plurality of cutting lanes—the cutting lanes include a first cutting lane, a second cutting lane, and a third cutting lane, wherein the first cutting lane and the second cutting lane are arranged parallel to each other, the third cutting lane is arranged intersecting the first cutting lane and the second cutting lane, and a die test structure is arranged in the first cutting lane—; and a method for manufacturing a chip comprising cutting the semiconductor device into a plurality of chips along the first cutting lane, the second cutting lane, and the third cutting lane. In some embodiments, cutting a semiconductor device into a plurality of chips along a first cutting lane, a second cutting lane and a third cutting lane includes cutting the semiconductor device twice with two different cutting processes. In some embodiments, cutting a semiconductor device into a plurality of chips along a first cutting lane,