KR-102963514-B1 - METHOD FOR SIMULATING SEMICONDUCTOR DEVICE

KR102963514B1KR 102963514 B1KR102963514 B1KR 102963514B1KR-102963514-B1

Abstract

The present invention comprises extracting a Hamiltonian and a superposition matrix of a semiconductor device using density functional theory or a strongly coupled method; calculating Bloch states for each corresponding energy based on the Hamiltonian, the superposition matrix, and an energy-wavenumber relationship within an effective energy region; and applying the Hamiltonian and the superposition matrix to a transformation matrix orthogonalized to a matrix representing the Bloch states to obtain a first reduced Hamiltonian and a first reduced superposition matrix with a reduced matrix size; The present invention provides a method for simulating a semiconductor device, comprising comparing a first energy band structure calculated based on the Hamiltonian and the superposition matrix with a second energy band structure calculated based on the first reduced Hamiltonian and the first reduced superposition matrix, and calculating a final transformation matrix and a final energy band structure in which all non-physical branches, which are energy bands not corresponding to the first energy band structure, are removed from the second energy band structure within the effective energy region, wherein the semiconductor device includes a source region, a drain region, and a channel region between the source region and the drain region, and the channel region includes a plurality of unit cells having different materials or different structures.

Inventors

신민철
전성혁

Assignees

한국과학기술원

Dates

Publication Date: 20260513
Application Date: 20201105

Claims (15)

In a method for simulating semiconductor devices using a processor, Extracting the Hamiltonian and overlap matrix of a semiconductor device using density functional theory (DFT) or the tight-binding (TB) method; Calculating Bloch states for each corresponding energy within the effective energy region based on the Hamiltonian, the overlap matrix, and the energy-wavenumber relationship; Applying the Hamiltonian and the superposition matrix to a transformation matrix orthonormalized from the matrix representing the Bloch states to obtain a first reduced Hamiltonian and a first reduced superposition matrix with reduced matrix sizes; and Comparing a first energy band structure calculated based on the Hamiltonian and the superposition matrix with a second energy band structure calculated based on the first reduced Hamiltonian and the first reduced superposition matrix, and calculating a final transformation matrix and a final energy band structure in which all unphysical branches (UPBs), which are energy bands that do not correspond to the first energy band structure, are removed from the second energy band structure within the effective energy region, wherein The semiconductor device includes a source region, a drain region, and a channel region between the source region and the drain region. The above channel region includes a plurality of unit cells having different materials or different structures, and The above plurality of unit cells include a first unit cell and a second unit cell, and The above first unit cell has a first Hamiltonian, The above second unit cell is a method for simulating a semiconductor device having a second Hamiltonian different from the first Hamiltonian.
In Article 1, The above unit cells further include a third unit cell positioned at the center of the channel region, and A method for simulating a semiconductor device in which the first and second unit cells have a symmetrical structure with respect to the third unit cell.
In Article 1, The above unit cells further include a third unit cell positioned at the center of the channel region, and A method for simulating a semiconductor device in which the first and second unit cells have an asymmetric structure with respect to the third unit cell.
In Article 1, Removing the aforementioned non-physical branches is: Examining whether the non-physical branches exist within the effective energy region of the periodic supercell structure including the unit cells; and A method for simulating a semiconductor device by repeating band calculations while sequentially changing the unit cells when the above non-physical branches exist.
In Article 1, Calculating the above final transformation matrix and the above final energy band structure is: Calculating the number of second eigenvalues, which is the number of eigenvalues included in the second energy band structure; Comparing the number of first eigenvalues, which is the number of eigenvalues included in the first energy band structure, with the number of second eigenvalues; If the number of the second eigenvalues is greater than the number of the first eigenvalues, generating an additional basis that removes the non-physical branches from the effective energy region and adding it to the transformation matrix; and A method for simulating a semiconductor device comprising determining the transformation matrix with the additional basis added as the final transformation matrix when the number of the second eigenvalues converges to the number of the first eigenvalues.
In Article 5, Adding the above additional basis to the above transformation matrix is: Recalculating the number of the second eigenvalues in the energy band by the intermediate transformation matrix to which the above additional basis has been added; and A method for simulating a semiconductor device comprising, when the number of the second eigenvalues recalculated is greater than the number of the first eigenvalues, generating a new additional basis that removes the non-physical branches from the effective energy region and adding it to the transformation matrix.
In Article 5, A method for simulating a semiconductor device, wherein adding the additional basis to the transformation matrix is performed by recalculating the second eigenvalue until the number of the second eigenvalues converges to the number of the first eigenvalues, and repeating the process of generating the additional basis and adding it to the transformation matrix.
In Article 7, A simulation method for a semiconductor device generated based on a variable vector calculated through a minimization function, wherein the additional basis is such that the absolute value of the difference between the number of second eigenvalues by the i-th transformation matrix to which the i-th (where i is a natural number) additional basis is applied and the number of second eigenvalues by the (i-1)-th transformation matrix to which the (i-1)-th additional basis is applied is maximized.
In Article 1, Obtaining the first reduced Hamiltonian and the first reduced overlap matrix is: Generating a normalized orthogonal basis that orthogonalizes the matrix representing the above Bloch states; Outputting the transformation matrix by removing states having values less than or equal to a reference value set in the above orthogonal basis; and A method for simulating a semiconductor device comprising applying the Hamiltonian and the overlap matrix to the transformation matrix to output the first reduced Hamiltonian and the first reduced overlap matrix.
In Article 1, A method for simulating a semiconductor device in which the above effective energy region is set based on at least one of a conduction band edge and a valence band edge depending on the type of semiconductor device.
In Article 1, A simulation method for a semiconductor device in which the above Bloch states are each calculated using an eigenvalue solution method for the Schrödinger equation from the above Hamiltonian and the above superposition matrix.
In Article 1, A method for simulating a semiconductor device, further comprising calculating the current characteristics of the semiconductor device based on a second reduced Hamiltonian and a first reduced superposition matrix in which an initial potential, which is a predetermined external potential component, is added to the first reduced Hamiltonian and the first reduced superposition matrix.
In Article 12, Calculating the current characteristics of the above semiconductor device is: Obtaining the second reduced Hamiltonian based on the first reduced Hamiltonian, the first reduced superposition matrix, and the initial potential; Calculating electron density by applying the second reduced Hamiltonian and the first reduced superposition matrix to a non-equilibrium Green's function (NEGF); Updating the initial potential by applying the above electron density to Poisson's equation; Calculating the potential difference between the initial potential and the updated potential of the second reduced Hamiltonian; When the above potential difference is below a predetermined threshold value, calculating the current density and current using the updated potential; and A method for simulating a semiconductor device, comprising updating the second reduced Hamiltonian with the updated potential when the potential difference exceeds the threshold value.
In Article 13, A simulation method for a semiconductor device that updates the potential and the second reduced Hamiltonian by repeating the solution of the Poisson equation and the non-equilibrium Green's function in a self-consistent manner until the potential difference converges to below the threshold value.
In Article 1, A method for simulating a semiconductor device, wherein the above semiconductor device is a field effect transistor (FET) having a bulk, ultra-thin body (UTB), fin, nanowire, gate-all-around (GAA) structure, etc.

Description

Method for Simulating Semiconductor Devices The present invention relates to a method for simulating a semiconductor device, and more specifically, to a method for simulating a semiconductor device having a heterogeneous structure. As research and development progresses in the high integration and miniaturization of transistors, transistors using CMOS manufacturing technology of 100 nm or less are being commercialized. Furthermore, recently, technologies to form transistor channel lengths as short as 10 nm or less are being developed, and there is a trend of research and development in 3D device manufacturing processes such as Ultra-thin-body (UTB), FinFET, and Gate-all-around (GAA) FET. As channel lengths shrink to the nanometer level, the number of atoms within the device becomes limited to only a few hundred to a few thousand. Consequently, the influence of interactions between single atoms increases, making an atomic-level modeling approach essential. This can be achieved through quantum mechanics simulations based on the wave nature of electrons, specifically the Schrödinger equation. Meanwhile, in simulations, the size of the Hamiltonian, which contains atomic information, is proportional to the number of atoms and orbitals within a unit cell. Therefore, when simulations are applied to currently developed transistor devices, matrix calculations of millions by millions are performed, requiring very large amounts of memory and inevitably consuming computation time. Accordingly, research is underway to reduce the memory and time required for computation by decreasing the size of the Hamiltonian. FIG. 1 is a flowchart for explaining a method for simulating a semiconductor device according to embodiments of the present invention. FIG. 2 is a conceptual diagram showing a part of a semiconductor device that is the subject of a simulation method according to embodiments of the present invention. FIG. 3 is a flowchart for specifically explaining a method for calculating a final transformation matrix and a final energy band structure in a simulation method of a semiconductor device according to embodiments of the present invention. FIG. 4 is a flowchart for explaining a method for simulating a semiconductor device according to embodiments of the present invention. FIG. 5 is a flowchart for specifically explaining a method for calculating current characteristics in a simulation method of a semiconductor device according to embodiments of the present invention. FIGS. 6 and 7 are graphs for explaining the energy band structure calculated according to the simulation method of a semiconductor device according to embodiments of the present invention. In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. The present invention is not limited to the embodiments disclosed below, but can be implemented in various forms and subject to various modifications and changes. The description of the embodiments is provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention. For convenience of explanation in the attached drawings, the proportions of each component may be exaggerated or reduced. The terms used in this specification are for describing embodiments and are not intended to limit the invention. Furthermore, unless otherwise defined, the terms used in this specification may be interpreted in the sense commonly known to those skilled in the art. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text. As used in this specification, ‘comprises’ and/or ‘comprising’ do not exclude the presence or addition of one or more other components, steps, actions, and/or elements to the mentioned components, steps, actions, and/or elements. Although terms such as "first," "second," etc., have been used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by such terms. These terms are used merely to distinguish one specific region, direction, or shape from another region, direction, or shape. Accordingly, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment. The embodiments described and illustrated herein also include their complementary embodiments. Throughout the specification, parts indicated by the same reference numeral represent the same components. Hereinafter, a method for simulating a semiconductor device according to embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a flowchart for explaining a method for simulating a semiconductor device according to embodiments of the present invention. Referring to FIG. 1, a simulation method for a s