KR-102963529-B1 - Inter-level handshake for high-density 3D logic integration

Abstract

A semiconductor device includes a first device plane on a substrate. The first device plane includes a first transistor device having a first source/drain (S/D) region formed in an S/D channel. A second device plane is formed on the first device plane. The second device plane includes a second transistor device having a second gate formed in a gate channel adjacent to the S/D channel. A first inter-level connection is formed from the first S/D region of the first transistor device to the second gate of the second transistor device. The first inter-level connection includes a lateral offset from the S/D channel to the gate channel.

Inventors

• 리브만 라스
• 스미스 제프리
• 샤네모우게임 다니엘
• 구트윈 폴

Assignees

• 도쿄엘렉트론가부시키가이샤

Dates

Publication Date

20260511

Application Date

20211013

Priority Date

20210524

Claims (16)

1. As a semiconductor device, A first device plane on a substrate, wherein the first device plane comprises a first transistor device having a first source/drain (S/D) region formed in a source/drain (S/D) channel; A second device plane on the first device plane, wherein the second device plane comprises a second transistor device having a second gate formed in a gate channel adjacent to the S/D channel; and A first level-to-level connection portion from a first S/D region of the first transistor device to a second gate of the second transistor device, wherein the first level-to-level connection portion includes a lateral offset from the S/D channel to the gate channel. Includes, The first level-to-level connection includes the S/D channel, a horizontal portion in contact with the S/D channel, and a vertical portion connecting the horizontal portion to the second gate. The above vertical portion extends from the first device plane to the second device plane and corresponds to the vertical distance from the first S/D region to the second gate with respect to the surface of the substrate, and A semiconductor device comprising a p-type FET and an n-type FET positioned vertically relative to each other, wherein both the first transistor device and the second transistor device are complementary field-effect transistors (CFETs), and each CFET forms a vertical stack of at least four FETs on the surface of the substrate.
2. A semiconductor device according to claim 1, wherein the horizontal portion corresponds to the lateral offset.
3. A semiconductor device according to claim 1, wherein the first level-to-level connection portion has an L-shape in a horizontal cross-section parallel to the surface of the substrate.
4. A semiconductor device according to claim 1, wherein the first level-to-level connection portion includes a conductive metal wiring structure portion.
5. A semiconductor device according to claim 1, wherein the first transistor device is configured to provide an input signal to the second transistor device.
6. A semiconductor device according to claim 1, further comprising a second inter-level connection portion that connects the first gate of the first transistor device to the second S/D region of the second device plane.
7. In claim 6, the semiconductor device, wherein the second S/D region is part of the second transistor device in the second device plane.
8. In claim 6, the semiconductor device wherein the second S/D region is part of a third transistor device in the second device plane.
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11. A semiconductor device according to claim 1, wherein the vertical portion is in direct contact with the horizontal portion.
12. A semiconductor device according to claim 1, wherein the vertical portion is configured to electrically connect the horizontal portion to the second gate.
13. As a semiconductor device, A CFET pair formed on a substrate, wherein the CFET pair includes an upper CFET positioned above a lower CFET, and each CFET includes a p-type FET and an n-type FET positioned vertically above each other to form a vertical stack of at least four FETs with respect to the surface of the substrate; and A semiconductor device having a level-to-level connection from a complementary gate pair formed in the gate channel of one CFET to an S/D region formed in the S/D channel of another CFET, wherein the gate channel of the one CFET has a lateral offset from the S/D channel of the other CFET in a horizontal direction along the surface of the substrate, and a vertical distance from the S/D channel of the other CFET in a vertical direction relative to the surface of the substrate.
14. In Clause 13, the above-mentioned inter-level connection part is, The above S/D channel; A horizontal portion connected to the above S/D channel and corresponding to the above lateral offset, and Connecting the above horizontal part to the gate channel and the vertical part corresponding to the vertical distance A semiconductor device including
15. In paragraph 13, the gate is a semiconductor device that occupies each recessed channel.
16. A semiconductor device according to claim 13, wherein the level-to-level connection is formed from the upper complementary gate pair of the upper CFET to the lower S/D region of the lower CFET, and the semiconductor device further comprises a self-aligned contact connecting the upper complementary gate pair to one or more structural parts located below the upper complementary gate pair.

Description

Inter-level handshake for high-density 3D logic integration Merging by reference The present invention claims the benefit of U.S. Provisional Application No. 63/121,845 (filed December 4, 2020) and U.S. Regular Application No. 17/328,289 (filed May 24, 2021) (the full contents of these applications are incorporated herein). Technology field The present invention relates to a microelectronic device comprising a semiconductor device, a transistor, and an integrated circuit, and a micromanufacturing method. When manufacturing semiconductor devices (especially on a microscopic scale), various manufacturing processes such as film deposition, etching mask generation, patterning, material etching and removal, and doping are executed. These processes are performed repeatedly to form desired semiconductor device elements on a substrate. Historically, through microfabrication, transistors were created on a single plane along with wiring/metallization formed on the active device plane, and were thus characterized as two-dimensional (2D) circuits or 2D fabrication. Although scaling efforts significantly increased the number of transistors per unit area of 2D circuits, scaling efforts faced greater challenges as the semiconductor device manufacturing node entered the single-digit nanometer range. Semiconductor device manufacturers expressed a demand for three-dimensional (3D) semiconductor circuits in which transistors are stacked vertically on top of each other. The technology forming the background of the present invention is disclosed in U.S. Patent Application Publication US2020/0111798 (April 9, 2020). The present invention relates to a semiconductor device. An embodiment (1) includes a semiconductor device. The semiconductor device includes a first device plane on a substrate. The first device plane includes a first transistor device having a first source/drain (S/D) region formed in a source/drain (S/D) channel. A second device plane is formed on the first device plane. The second device plane includes a second transistor device having a second gate formed in a gate channel adjacent to the S/D channel. A first level-to-level connection is formed from the first S/D region of the first transistor device to the second gate of the second transistor device. The first level-to-level connection includes a lateral offset from the S/D channel to the gate channel. The embodiment (2) includes a semiconductor device in the embodiment (1), wherein the first level-to-level connection portion comprises an S/D channel, a horizontal portion in contact with the S/D channel, and a vertical portion connecting the horizontal portion to a second gate. The embodiment (3) includes a semiconductor device in which the horizontal portion corresponds to a lateral offset in the embodiment (2). The embodiment (4) includes a semiconductor device in the embodiment (2), wherein the vertical portion extends from the first device plane to the second device plane and corresponds to the vertical distance from the first S/D region to the second gate with respect to the surface of the substrate. The embodiment (5) includes a semiconductor device in the embodiment (2), wherein the first level connection portion has an L shape in a horizontal cross-section parallel to the surface of the substrate. An embodiment (6) includes a semiconductor device in which, in embodiment (1), the first level connection portion includes a conductive metal wiring structure portion. The embodiment (7) includes a semiconductor device in which, in the embodiment (1), the first transistor device is configured to provide an input signal to the second transistor device. An embodiment (8) includes a semiconductor device that, in embodiment (1), further includes a second level-to-level connection portion that connects the first gate of the first transistor device to the second S/D region of the second device plane. In the embodiment (9), the second S/D region in the embodiment (8) includes a semiconductor device that is part of a second transistor device in the second device plane. In the embodiment (10), the second S/D region in the embodiment (8) includes a semiconductor device that is part of a third transistor device in the second device plane. The embodiment (11) includes a semiconductor device in which, in the embodiment (1), the first transistor device and the second transistor device are both complementary field-effect transistors (CFETs). An embodiment (12) comprises a semiconductor device in which, in embodiment (1), the first transistor device is an n-type field-effect transistor (FET). The second transistor device is a p-type FET, and the first device plane further comprises another n-type FET to form a CFET with the second transistor device. A semiconductor device is provided according to an embodiment (13) of the present invention. The semiconductor device includes a pair of CFETs formed on a substrate. The pair of CFETs includes an upper CFET positioned above a lowe