KR-102963610-B1 - Socket for testing semiconductor package
Abstract
A semiconductor test socket is disclosed. A semiconductor test socket according to one aspect of the present invention may include: a lower body mounted on a substrate and having a first receiving space formed therein; a pin plate positioned within the first receiving space of the lower body, supported by the lower body, and having a plurality of contact pins arranged therein that contact terminals of a semiconductor chip; an upper body elastically supported on the upper side of the lower body and having a second receiving space formed therein that communicates with the first receiving space; a latch portion that presses and fixes a semiconductor chip in contact with a contact pin of the pin plate; and a floating adapter portion that guides the position of a semiconductor chip in contact with a contact pin of the pin plate, and guides the latch portion to move in a vertical direction when the latch portion touches the semiconductor chip to press the semiconductor chip.
Inventors
- 전진국
- 이찬호
- 이용관
Assignees
- 주식회사 오킨스전자
Dates
- Publication Date
- 20260513
- Application Date
- 20230927
Claims (8)
- A lower body mounted on a substrate and having a first receiving space formed inside; A pin plate having a plurality of contact pins arranged thereon, which are positioned inside the first receiving space of the lower body, supported by the lower body, and contact the terminals of a semiconductor chip; An upper body elastically supported on the upper side of the lower body and having a second receiving space formed therein that communicates with the first receiving space; A latch portion that fixes a semiconductor chip in contact with a contact pin of the above-mentioned pin plate by applying pressure; A floating adapter part that guides the position of a semiconductor chip in contact with a contact pin of the above-mentioned pin plate, and guides the latch part to move in a vertical direction when the latch part contacts the semiconductor chip to apply pressure to the semiconductor chip; Includes, The above latch part is, A first arm, one end of which is hinge-connected to the upper body and extends to the upper side of the area where the semiconductor chip is located; A pad hinge-coupled to the other end of the first arm and forming a flat pressing surface on the surface facing the pin plate to contact the upper surface of the semiconductor chip; One end is hinge-connected to the lower body, and the other end is a second arm hinge-connected between the one end and the other end of the first arm; Includes, A slit is formed on the side of the pad so as to have a longitudinal direction parallel to the upper surface of the semiconductor chip, and It is movable and rotatably coupled along the longitudinal direction of the above slit and includes a first axis coupled to the first arm, The above floating adapter part is, A first floating adapter having a semiconductor position portion into which a semiconductor chip contacting a contact pin of the pin plate is inserted, and elastically supported by the pin plate or the lower body, and compressed toward the pin plate by the pressure when the latch portion presses the semiconductor chip located in the semiconductor position portion; A second floating adapter disposed between the first floating adapter and the pin plate, elastically supported by the pin plate or the lower body, compressed toward the pin plate by the pressure when the latch portion presses the semiconductor chip located at the semiconductor position portion, and aligns the pressure surface of the pad parallel to the semiconductor chip before the pad of the latch portion contacts the upper surface of the semiconductor chip; A semiconductor test socket including
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- In paragraph 1, The above pad is, A pressure member formed such that the pressure surface is formed at a point extending inwardly from the point hinge-connected to the first arm; A projection extending in a direction parallel to the axis hinged to the first arm at a point spaced inwardly from the point hinged to the first arm of the above-mentioned pressurizing part; A semiconductor test socket including
- In paragraph 4, The above-mentioned second floating adapter is, A frame positioned below the semiconductor position portion of the first floating adapter, formed larger than the outer edge of the semiconductor position portion along the outer edge of the semiconductor position portion, and elastically supported by the pin plate or the lower body; A semiconductor test socket comprising: a vertical movement guide protruding from the side of the frame so as to come into contact with the protrusion of the pad before the semiconductor chip when the pad descends to press the semiconductor chip.
- In paragraph 5, The above vertical movement interior is, A semiconductor test socket comprising a vertical movement guide projection formed protruding from the second floating adapter such that when the socket of the pad reaches the upper side of the semiconductor chip to fix the semiconductor chip, it comes into contact with the socket, thereby restricting the horizontal movement of the socket and allowing it to move only in the vertical direction.
- In paragraph 6, A semiconductor test socket, wherein the vertical movement guide projection is formed to protrude to a position higher than the height of the semiconductor chip located at the semiconductor position.
- In paragraph 6, The above vertical movement guide projection is formed such that the side contacting the projection is perpendicular to the semiconductor chip, and A semiconductor test socket, wherein the side of the protrusion of the pad in contact with the vertical movement guide protrusion is formed to be perpendicular to the semiconductor chip.
Description
Socket for testing semiconductor package The present invention relates to a semiconductor test socket, and more specifically, to a semiconductor test socket capable of preventing scratches when mounting a semiconductor chip in the semiconductor test socket. After undergoing the manufacturing process, semiconductor devices are subjected to testing to evaluate their electrical performance. Performance testing is performed by inserting a semiconductor chip test socket, designed to make electrical contact with the device's terminals, between the device and a test circuit board. In addition to testing semiconductor devices, the semiconductor chip test socket is also used during the burn-in testing process in the manufacturing process. During the semiconductor testing process, semiconductor chips are mounted into test sockets while still packaged; therefore, it is crucial to reliably achieve this mounting of the semiconductor into the socket. Figures 1 and 2 are drawings illustrating the mounting of a semiconductor in a conventional general semiconductor test socket. As illustrated in FIGS. 1 and 2, a conventional semiconductor test socket may be provided with a lower body (20) mounted on a test substrate, a pin plate (30) provided on the inside of the lower body (20) and having pins arranged thereon to contact the semiconductor to be tested, and an upper body (40) elastically supported on the upper side of the lower body (20). In addition, a floating adapter (50) that guides the position of the semiconductor chip (1) can be elastically supported on the upper side of the pin plate (30). In addition, a latch (60) for fixing the semiconductor chip (1) located on the floating adapter (50) may be provided. As shown in FIGS. 1 and 2, the above latch (60) is composed of an arm (62) hinged to the lower body (20) and the upper body (40) and a pad (64) hinged to the arm (62), and the pad (64) can move in an arc by the rotation of the hinge to compress and fix the semiconductor chip (1). At this time, when the pad (64) presses and fixes the semiconductor chip (1), it moves in an arc while pressing and fixing the semiconductor chip (1), and since the pad (64) also comes into contact with the semiconductor chip (1) in a state that is not horizontal, scratches may occur on the upper surface of the package of the semiconductor chip (1). Fine particles caused by scratches generated in this way remain on the surface of the semiconductor chip (1) and may have an adverse effect during subsequent processes, or may become a source of dissatisfaction due to scratch marks when delivering the semiconductor chip (1) after the burning test to a customer, so countermeasures are required. FIG. 1 is a cross-sectional view illustrating a conventional semiconductor test socket. FIG. 2 is a cross-sectional view illustrating a semiconductor chip being compressed and fixed in a conventional semiconductor test socket. FIG. 3 is a drawing illustrating a semiconductor test socket according to one embodiment of the present invention. FIG. 4 is a diagram showing a disassembled view of some parts of a semiconductor test socket according to one embodiment of the present invention. FIG. 5 is a diagram showing another part of a semiconductor test socket according to one embodiment of the present invention disassembled. FIG. 6 is a perspective view illustrating a pad of a semiconductor test socket according to one embodiment of the present invention. FIG. 7 is a perspective view illustrating a second floating adapter of a semiconductor test socket according to an embodiment of the present invention. FIGS. 8 to 10 are drawings illustrating the process of a semiconductor chip being compressed and fixed in a semiconductor test socket according to an embodiment of the present invention, where FIG. 8 is a drawing illustrating a state in which a pad approaches the upper side of a semiconductor chip while the semiconductor chip is placed on a first floating adapter. FIG. 9 is a diagram illustrating a state in which a pad is in contact with the upper surface of a semiconductor chip while the semiconductor chip is placed on a first floating adapter. FIG. 10 is a diagram illustrating a state in which a semiconductor chip is placed on a first floating adapter and the pad is compressed with the semiconductor chip and the floating adapter part. FIGS. 11 to 14 are drawings illustrating the movement of a pad during the process of a semiconductor chip being compressed and fixed in a semiconductor test socket according to an embodiment of the present invention, and FIG. 11 is a drawing illustrating the appearance of a pad approaching the upper side of a semiconductor chip while drawing an arc while the semiconductor chip is placed on a first floating adapter. FIG. 12 is a diagram illustrating a pad that approaches the upper side of a semiconductor chip and comes into contact with a vertical movement guide projection, thereby restricting horizontal movement and allowing mo