KR-102963624-B1 - Intersection array refresh method

KR102963624B1KR 102963624 B1KR102963624 B1KR 102963624B1KR-102963624-B1

Abstract

A technique for refreshing threshold switching selectors in programmable resistive memory cells of a crossover memory array is disclosed herein. The Vt of the threshold switching selectors may drift over time. The memory system resets the Vt of the threshold switching selectors by a selector refresh operation and refreshes the data of the programmable resistive memory elements using a separate data refresh operation. The data refresh operation itself may refresh the selectors. However, the threshold switching selector refresh operation is faster than the data refresh operation. Furthermore, the threshold switching selector refresh operation consumes almost no power and/or current as the data refresh operation. Therefore, the selector refresh operation can be performed at a faster rate than the data refresh operation.

Inventors

트란, 마이클 니콜라스 앨버트
그로비스, 마이클 케이.
파킨슨, 워드
프랭클린, 나탄

Assignees

샌디스크 테크놀로지스 아이엔씨.

Dates

Publication Date: 20260513
Application Date: 20230503
Priority Date: 20220525

Claims (20)

As a device, One or more control circuits configured to communicate with one or more intersection arrays, each array comprising a plurality of first conductive lines, a plurality of second conductive lines, and a programmable resistive memory cell, each programmable resistive memory cell comprising a programmable resistive memory element in series with a two-terminal threshold switching selector having a threshold voltage, each memory cell being connected between a first conductive line of one of the first conductive lines and a second conductive line of one of the second conductive lines, and the one or more control circuits Turning on the threshold switching selector of the selected programmable resistive memory cell and reading the selected programmable resistive memory cell by keeping the threshold switching selector on for a first time period to read the state of the programmable resistive memory element of the selected programmable resistive memory cell; and A device configured to refresh the threshold switching selector of the selected programmable resistive memory cell by turning on the threshold switching selector of the selected programmable resistive memory cell and keeping the threshold switching selector on for a second time period shorter than the first time period for resetting the threshold voltage of the threshold switching selector.
In paragraph 1, the above one or more control circuits are, Refreshing the threshold switching selector of each programmable resistive memory cell at a first rate and—including turning on the threshold switching selector by applying signals to a specific programmable resistive memory cell to reset the threshold voltage of the threshold switching selector—; and A device configured to refresh the programmable resistive memory elements of each programmable resistive memory cell at a second speed lower than the first speed, including applying signals to a specific programmable resistive memory cell to refresh the data stored in the programmable resistive memory elements of a specific programmable resistive memory cell.
In paragraph 1, the above one or more control circuits are, A device configured to apply a signal to the selected programmable resistor memory cell for a predetermined period to turn on a threshold switching selector and keep the threshold switching selector on for a second period.
In paragraph 1, the above one or more control circuits are, Applying a signal to the selected programmable resistor memory cell to turn on the threshold switching selector; Detecting that the threshold switching selector has been turned on in response to a signal; and A device configured to turn off the threshold switching selector by removing a signal from the selected programmable resistor memory in response to detecting that the threshold switching selector has been turned on, in order to keep the threshold switching selector on during a second period.
In paragraph 1, the above one or more control circuits are, i) Select a selector refresh group for refreshing a threshold switching selector of each programmable resistive memory cell within the selector refresh group - said selector refresh group comprises a plurality of programmable resistive memory cells of one or more intersection arrays -; ii) reset the threshold voltage of the threshold switching selector of each programmable resistor memory cell within the selected selector refresh group without refreshing the data stored in the programmable resistor memory cell; iii) repeat i) and ii) for other selector refresh groups of one or more intersection arrays; and iv) A device configured to periodically refresh the threshold switching selector of each selector refresh group by repeating i), ii), and iii) at regular intervals.
In paragraph 5, a device configured such that each selector refresh group stores a plurality of ECC codewords.
In paragraph 5, a device configured such that each selector refresh group stores an ECC crossword.
In paragraph 1, the above one or more control circuits are, Simultaneously turning on the first threshold switching selector of the first programmable resistive memory cell selected for reading and the second threshold switching selector of the second programmable resistive memory cell selected for threshold switching selector refresh; After resetting Vt of the second threshold switching selector, turn off the second threshold switching selector of the second programmable resistor memory cell; and A device configured to keep the first threshold switching selector in the ON state while reading the first programmable resistor memory cell after turning off the second threshold switching selector.
In paragraph 8, the above one or more control circuits are, Driving current through a selected first conductive line connected to both the first memory cell and the second memory cell while turning on the second threshold switching selector by applying a selection voltage to a first bit line connected to the first memory cell and a second bit line connected to the second memory cell, and simultaneously turning on the first threshold switching selector; The refresh operation for the second threshold switching selector is terminated by changing the selection voltage applied to the second bit line to a non-selection voltage; and A device configured to read the first memory cell by maintaining the selection voltage applied to the first bit line at the selection voltage while continuously driving current through the selected first conductive line.
In paragraph 1, the above one or more control circuits are, During a refresh operation to refresh the threshold switching selector of a selected programmable resistive memory cell, current is forced through a selected first conductive line connected to the selected programmable resistive memory cell to turn on the threshold switching selector of the selected programmable resistive memory cell; and A device configured to terminate the refresh operation by removing the above current to turn off the threshold switching selector.
In paragraph 1, the above one or more control circuits are, During a refresh operation for refreshing a threshold switching selector of a selected programmable resistive memory cell, a voltage is applied to a selected first conductive line connected to the selected programmable resistive memory cell to turn on the threshold switching selector of the selected programmable resistive memory cell; and A device configured to terminate the refresh operation by removing the above voltage and turning off the threshold switching selector.
In paragraph 1, The above-mentioned programmable resistive memory element includes a magnetic tunnel junction (MTJ); The above threshold switching selector is a device comprising an ovonic threshold switch (OTS).
A method for refreshing a magnetoresistive memory cell (MRAM cell) of a memory structure having one or more intersection arrays, wherein each MRAM cell has a magnetoresistive element connected in series with a threshold switching selector having a threshold voltage at which the threshold switching selector is turned on, and the method comprises: A step of refreshing the threshold switching selector of each MRAM cell at a first speed - including turning on the threshold switching selector by applying first signals to a specific MRAM cell to reset the threshold voltage of the threshold switching selector -; and A method for refreshing a magnetoresistive memory cell of a memory structure having one or more intersection arrays, comprising the step of refreshing a magnetoresistive element of each MRAM cell at a second speed lower than a first speed, and the step of refreshing data stored in the magnetoresistive element of a specific MRAM cell by applying second signals to a specific MRAM cell.
In paragraph 13, the step of refreshing the threshold switching selector of each MRAM cell at the first rate and the step of refreshing the magnetoresistance element of each MRAM cell at the second rate are, for a plurality of repetitions, A step of turning on the threshold switching selector by applying the first signals to the specific MRAM cell for n times of each iteration to reset the threshold voltage of the threshold switching selector without refreshing the data stored in the magnetoresistance element of the specific MRAM cell; and A method for refreshing a magnetoresistive memory cell of a memory structure having one or more intersection arrays, comprising the step of, for each iteration, applying the first signal and the second signal to the specific MRAM cell for both turning on the threshold switching selector to reset the threshold voltage of the threshold switching selector and refreshing data stored in the magnetoresistive element of the specific MRAM cell.
As a memory system, A memory structure having a plurality of intersection arrays—each intersection array comprises a plurality of first conductive lines, a plurality of second conductive lines, and a magnetoresistive memory (MRAM) cell, each MRAM cell comprises a magnetoresistive memory element connected in series with a threshold switching selector, and each memory cell is connected between a first conductive line of one of the first conductive lines and a second conductive line of one of the second conductive lines—; and It includes one or more control circuits communicating with the above memory structure, and the one or more control circuits are: i) Select a selector refresh group - each selector refresh group includes at least one memory cell of a plurality of intersection array groups -; ii) without refreshing the data stored in the MRAM cell, reset the threshold voltage of the threshold switching selector of each MRAM cell of the selected selector refresh group; iii) repeat i) and ii) for a plurality of different selector refresh groups; and iv) A memory system configured to periodically refresh a threshold switching selector of the memory structure by repeating i), ii), and iii) at regular intervals.
In paragraph 15, the above one or more control circuits are: Refresh the above threshold switching selector at a first refresh rate; and A memory system configured to refresh data stored in the MRAM cells of the above memory structure at a second refresh rate smaller than the first refresh rate.
In paragraph 15, the above one or more control circuits are: A memory system configured to apply a signal to the MRAM cells of the selected selector refresh group for a predetermined period to reset the threshold voltage of each threshold switching selector of the MRAM cells of the selected selector refresh group without turning on each of the threshold switching selectors to refresh the data stored in the MRAM cells.
In claim 15, a memory system wherein each selector refresh group maintained by one or more control circuits comprises memory cells configured to store a plurality of ECC codewords.
In paragraph 15, a memory system wherein each selector refresh group maintained by one or more control circuits comprises memory cells configured to store an ECC crossword.
In paragraph 15, the above one or more control circuits are, Turning on the second threshold switching selector of the second MRAM cell selected for threshold switching selector refresh, and simultaneously turning on the first threshold switching selector of the first MRAM cell selected for reading; After resetting the second threshold switching selector, turn off the second threshold switching selector; and A memory system configured to keep the first threshold switching selector in the ON state while reading the first MRAM cell after turning off the second threshold switching selector.

Description

Intersection array refresh method Cross-reference of related applications This application claims the benefit of U.S. Regular Application No. 17/824,806, filed on May 25, 2022, titled "CROSS-POINT ARRAY REFRESH SCHEME," the entire contents of which are incorporated herein by reference for all purposes. Memory is widely used in various electronic devices such as cellular phones, digital cameras, personal information terminals, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory may include non-volatile memory or volatile memory. Non-volatile memory enables information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). Memory cells may exist as an intersection memory array. In a memory array having an intersection type architecture, one set of conductive lines runs across the surface of the substrate, and another set of conductive lines runs across the substrate in a direction perpendicular to the other set of conductive lines and is formed over the other set of conductive lines. Memory cells are located at the intersection junctions of the two sets of conductive lines. Programmable resistive memory cells are formed from a material ("memory element") having programmable resistance. In a binary approach, a programmable resistive memory cell at each intersection can be programmed into one of two resistance states: high and low. In some approaches, more than two resistance states may be used. One type of programmable resistive memory cell is a magnetoresistive random access memory (MRAM) cell. In contrast to some other memory technologies that use electronic charges to store data, an MRAM cell uses magnetization to represent stored data. Data bits are written to the MRAM cell by changing the magnetization direction of the magnetic element ("free layer") within the MRAM cell, and bits are read by measuring the resistance of the MRAM cell (low resistance typically represents a "0" bit, and high resistance typically represents a "1" bit). In a crossover memory array, each memory cell may include a two-terminal threshold switching selector in series with the memory element. The threshold switching selector has high resistance (in the off or non-conductive state) until it is biased to a voltage higher than its threshold voltage (Vt) or a current exceeding its threshold current, and until its voltage bias drops below Vhold ("Voffset") or the current drops below the holding current (Ihold). After Vt is exceeded and while Vhold is exceeded across the threshold switching selector, the threshold switching selector has low resistance (in the on or conductive state). The threshold switching selector remains in the on state until its current drops below the holding current (Ihold) or the voltage drops below the holding voltage (Vhold). When this occurs, the threshold switching selector returns to the off (higher) resistance state. Thus, to program a memory cell at the crossover, a voltage sufficient to turn on the associated threshold switching selector and to set or reset the memory cell is applied. To read a memory cell, a threshold switching selector is similarly activated by turning on the resistance state of the memory cell before it can be determined. One embodiment of the threshold switching selector is an ovonic threshold switch (OTS). Data is stored in a group of programmable resistive memory cells as Error Correction Code (ECC) codewords. An ECC codeword includes data bits and a parity bit. After reading the ECC codeword, it is processed by an ECC decoder to detect and correct errors within the codeword. However, there is a limit to the number of errors that can be corrected. Over time, the physical conditions of programmable resistive memory elements can change slowly in relation to their ability to retain data ("data retention"). For example, the free-layer magnetization of an MRAM cell can change slowly, which can lead to data errors. To aid in data preservation, a data refresh operation may be performed. One type of data refresh operation can correct errors by reading an ECC codeword from a memory cell and decoding it. The corrected ECC codeword is then written back to the same group of memory cells or, optionally, to a different group. Such data refresh operations can take a significant amount of time, which prevents general users from accessing the memory array. Additionally, data refresh operations can consume significant power and/or current. Furthermore, data refresh is a cause of wear on memory cells, affecting their durability. Elements of similar drawing symbols refer to common components in different drawings. Figure 1 is a graph of the threshold switching selector Vt versus time. FIG. 2a is a block diagram of one embodiment of a memory die. FIG. 2b is a block diagram of one embodiment of an integrated memory assembly including a control die and a memory structure die. FIG. 3 is a blo