KR-102963650-B1 - Semiconductor package

Abstract

The present invention relates to a semiconductor package, and more specifically, may include a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, first bumps provided between the first redistribution substrate and the first semiconductor chip, a conductive structure provided on the first redistribution substrate and horizontally spaced apart from the first semiconductor chip, a second redistribution substrate on the first semiconductor chip, second bumps provided between the first semiconductor chip and the second redistribution substrate, a second semiconductor chip mounted on the second redistribution substrate, a first molding film provided between the first redistribution substrate and the second redistribution substrate and covering the first semiconductor chip, and a second molding film provided on the second redistribution substrate, covering the second semiconductor chip and spaced apart from the first molding film.

Inventors

• 최주일
• 강운병
• 윤민승
• 조용회
• 진정기
• 최윤석

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260512

Application Date

20211013

Claims (20)

1. Substrate; A first rewiring substrate on the above substrate; A first semiconductor chip mounted on the first rewiring board; First bumps provided between the first rewiring substrate and the first semiconductor chip; A first conductive structure provided on the first redistribution substrate and horizontally spaced from the first semiconductor chip; A second rewiring substrate on the first semiconductor chip above; Second bumps provided between the first semiconductor chip and the second rewiring substrate; A second semiconductor chip mounted on the second rewiring board above; A second conductive structure provided on the substrate and horizontally spaced from the first redistribution substrate; A first molding film provided between the first redistribution substrate and the second redistribution substrate to cover the first semiconductor chip; and It includes a second molding film provided on the second redistribution substrate, covering the second semiconductor chip, and spaced apart from the first molding film. The level of the lower surface of the second conductive structure is lower than the level of the upper surface of the first redistribution board, and A semiconductor package in which the level of the upper surface of the second conductive structure is higher than the level of the lower surface of the second redistribution substrate.
2. In Article 1, The first redistribution substrate includes a first insulating layer and a first redistribution pattern within the first insulating layer, and The first rewiring pattern includes a first seed pattern and a first conductive pattern on the first seed pattern, and The second redistribution substrate includes a second insulating layer and a second redistribution pattern within the second insulating layer. The above second rewiring pattern is a semiconductor package comprising a second seed pattern and a second conductivity pattern on the second seed pattern.
3. In Article 1, A semiconductor package in which the width of the first semiconductor chip is smaller than the width of the second semiconductor chip.
4. In Article 1, The first molding film fills the space between the first bumps, and The first molding film above is a semiconductor package that fills the space between the second bumps.
5. In Article 1, The first bumps above include solder balls or solder bumps, and The above second bumps are a semiconductor package including a pillar.
6. In Article 1, Third bumps provided between the second rewiring substrate and the second semiconductor chip; and A semiconductor package further comprising an underfill film interposed between the second rewiring substrate and the second semiconductor chip and filling the space between the third bumps.
7. In Article 1, It further includes third bumps provided between the second rewiring substrate and the second semiconductor chip, The second molding film above is a semiconductor package that fills the space between the third bumps.
8. In Article 1, The above-mentioned first semiconductor chip is: 1st chip substrate; A first upper wiring layer on the upper surface of the first chip substrate; A first lower wiring layer on the lower surface of the first chip substrate; and A semiconductor package including a through-via penetrating the first chip substrate.
9. In Article 1, A semiconductor package in which, from a planar perspective, the area of the first semiconductor chip is smaller than the area of the second semiconductor chip.
10. In Article 1, The above second molding film is a semiconductor package that exposes the upper surface of the above second semiconductor chip.
11. In Article 1, A semiconductor package in which the upper surface of the second molding film is located at a higher level than the upper surface of the second semiconductor chip.
12. First substrate; A first redistribution substrate on the first substrate, wherein the first redistribution substrate comprises a first insulating layer and a first redistribution pattern within the first insulating layer; A first semiconductor chip mounted on the first rewiring board; A first conductive structure provided on the first redistribution substrate and horizontally spaced from the first semiconductor chip; A second redistribution substrate on the first semiconductor chip, wherein the second redistribution substrate comprises a second insulating layer and a second redistribution pattern within the second insulating layer; A second semiconductor chip mounted on the second rewiring board; and A second conductive structure provided on the first substrate and horizontally spaced from the first redistribution substrate, comprising: The first rewiring pattern includes a first seed pattern and a first conductive pattern on the first seed pattern, and The level of the lower surface of the second conductive structure is lower than the level of the upper surface of the first redistribution board, and A semiconductor package in which the level of the upper surface of the second conductive structure is higher than the level of the lower surface of the second redistribution substrate.
13. In Article 12, A first molding film provided between the first redistribution substrate and the second redistribution substrate to cover the first semiconductor chip; A second molding film provided on the second rewiring substrate and covering the second semiconductor chip; and A semiconductor package further comprising a third molding film provided on the first substrate and covering the first molding film and the second molding film.
14. In Article 13, The third molding film is in direct contact with the side walls of the first molding film, and The above third molding film is a semiconductor package in direct contact with the sidewalls of the above second molding film.
15. In Article 12, The above second rewiring pattern is a semiconductor package comprising a second seed pattern and a second conductivity pattern on the second seed pattern.
16. In Article 15, The first substrate includes a third insulating layer and a third redistribution pattern within the third insulating layer, and The above third rewiring pattern is a semiconductor package comprising a third seed pattern and a third conductive pattern on the above third seed pattern.
17. In Article 16, A second substrate provided on the second semiconductor chip is further included, The second substrate includes a fourth insulating layer and a fourth redistribution pattern within the fourth insulating layer, and The above-mentioned fourth rewiring pattern is a semiconductor package comprising a fourth seed pattern and a fourth conductivity pattern on the fourth seed pattern.
18. First substrate; A first rewiring substrate on the first substrate; A first semiconductor chip mounted on the first rewiring board; A first conductive structure provided on the first redistribution substrate and horizontally spaced from the first semiconductor chip; A second rewiring substrate on the first semiconductor chip above; A second semiconductor chip mounted on the second rewiring board above; A second conductive structure provided on the first substrate and horizontally spaced from the first redistribution substrate; A second substrate on the second semiconductor chip; and A first molding film provided between the first redistribution substrate and the second redistribution substrate, covering the first semiconductor chip, wherein The first molding film is interposed between the first redistribution substrate and the first semiconductor chip, and between the first semiconductor chip and the second redistribution substrate, and The level of the lower surface of the second conductive structure is lower than the level of the upper surface of the first redistribution board, and A semiconductor package in which the level of the upper surface of the second conductive structure is higher than the level of the lower surface of the second redistribution substrate.
19. In Article 18, It further includes a third semiconductor chip mounted on the second substrate, The third semiconductor chip is a semiconductor package comprising a semiconductor chip of a different type from the first semiconductor chip and the second semiconductor chip.
20. In Article 18, A second molding film provided on the second rewiring substrate and covering the second semiconductor chip; and A third molding film provided on the first substrate and covering the second conductive structure is further included, The upper surface of the second molding film is located at the same level as the upper surface of the second semiconductor chip, and The third molding film is a semiconductor package interposed between the second semiconductor chip and the second substrate.

Description

Semiconductor package The present invention relates to a semiconductor package, and more specifically, to a semiconductor package including a redistribution substrate. A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting semiconductor chips onto a printed circuit board (PCB) and electrically connecting them using bonding wires or bumps. With the recent advancement of the electronics industry, semiconductor packages are evolving in various directions with the goals of improving reliability, miniaturization, high integration, and reducing manufacturing costs. Furthermore, as their application fields expand to include high-capacity storage, a wide variety of semiconductor packages are emerging. FIG. 1 is a plan view for illustrating a semiconductor package according to embodiments of the present invention. FIG. 2 is a drawing for explaining a semiconductor package according to embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 1. FIG. 3 is a drawing for illustrating a semiconductor package according to embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 1. FIG. 4 is a drawing for illustrating a semiconductor package according to embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 1. FIG. 5 is a plan view illustrating a semiconductor package according to embodiments of the present invention. FIG. 6 is a drawing for illustrating a semiconductor package according to embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 5. FIG. 7 is a drawing for illustrating a semiconductor package according to embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 5. FIG. 8 is a drawing for illustrating a semiconductor package according to embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 5. FIG. 9 is a plan view illustrating a semiconductor package according to embodiments of the present invention. FIG. 10 is a drawing for illustrating a semiconductor package according to embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 9. FIG. 11 is a drawing for illustrating a semiconductor package according to embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 9. FIGS. 12 to 24 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to embodiments of the present invention. Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings. FIG. 1 is a plan view illustrating a semiconductor package according to embodiments of the present invention. FIG. 2 is a cross-sectional view along I-I' of FIG. 1 illustrating a semiconductor package according to embodiments of the present invention. Referring to FIGS. 1 and 2, the semiconductor package (1) may include a first rewiring substrate (100), a second rewiring substrate (500), a first semiconductor chip (200), and a second semiconductor chip (300). The first redistribution substrate (100) may include a first insulating layer (101), a first redistribution pattern (120), a first under-bump pattern (150), and a first pad structure (130). The first insulating layer (101) may be a single layer or a plurality of stacked layers. In some embodiments, the interface between adjacent first insulating layers (101) may not be distinct. In other embodiments, the interface between adjacent first insulating layers (101) may be distinct. The number of stacked first insulating layers (101) is not limited to that illustrated and may vary in many ways. The first insulating layer (101) may include an insulating polymer or a photosensitive polymer. For example, the insulating polymer may include an epoxy-based polymer. For example, the photosensitive polymer may include at least one of a photosensitive polyimide, polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer. As an example, the first insulating layer (101) may include a PID (Photo Imageable Dielectric). The first under-bump pattern (150) may be provided within the first insulating layer (101). The first insulating layer (101) may cover the first under-bump pattern (150). The first insulating layer (101) may expose the lower surface of the first under-bump pattern (150). The first under-bump pattern (150) may be provided in multiple numbers, and the first under-bump patterns (150) may be spaced apart horizontally (for example, in a direction parallel to the upper surface of the first redistribution board (100)). The first under-bump patterns (150) may function as pads for external terminals (400) to be described later and may be electrically connected to the first redist