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KR-102963661-B1 - SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

KR102963661B1KR 102963661 B1KR102963661 B1KR 102963661B1KR-102963661-B1

Abstract

Embodiments of the present invention provide a semiconductor device and a method for manufacturing a semiconductor device, comprising a test pattern capable of measuring a gate line width without increasing the size of the semiconductor device. The test pattern of the semiconductor device according to the present embodiment may include a substrate comprising a plurality of active regions defined by a device isolation layer and spaced apart at a certain interval and aligned; a gate structure formed on the device isolation layer between adjacent active regions; a pair of metal wiring contacts formed in each of the active regions; and a metal wiring connecting the metal wiring contacts facing each other in adjacent active regions.

Inventors

  • 장헌용

Assignees

  • 에스케이하이닉스 주식회사

Dates

Publication Date
20260512
Application Date
20210107

Claims (20)

  1. A substrate comprising a plurality of active regions defined by a device isolation layer and spaced apart at regular intervals and aligned; A gate structure formed on the device isolation layer between the adjacent active regions; A pair of metal wiring contacts formed in each of the above active regions; and Metal wiring connecting the metal wiring contacts facing each other in adjacent active regions Includes, The above active region is It is composed of an island shape having a major axis and a minor axis, and is aligned at regular intervals in the major axis direction and the minor axis direction, and The above gate structure includes a zigzag shape, A semiconductor device having a test pattern in which the length extended in the long axis direction of the active region is greater than the length extended in the short axis direction of the active region.
  2. In paragraph 1, A semiconductor device having a test pattern further comprising a first node and a second node formed on both ends of the gate structure.
  3. In paragraph 1, A semiconductor device having a test pattern further comprising a third node and a fourth node formed on both ends of the metal wiring.
  4. In paragraph 1, The above active region has a long axis and a short axis, and The above gate structure is a semiconductor device having a test pattern including a bar shape extended in the short-axis direction of the active region.
  5. In paragraph 1, The above metal wiring is a semiconductor device having a test pattern including a bar shape.
  6. In paragraph 1, The above metal wiring is a semiconductor device having a test pattern comprising a chain pattern in which a plurality of metal wirings are arranged in a zigzag shape.
  7. In paragraph 1, A semiconductor device having a test pattern further comprising a doping region in which impurities are doped within the active region.
  8. In Paragraph 7, The above doping region is a semiconductor device having a test pattern containing N-type impurities or P-type impurities.
  9. In paragraph 1, The above gate structure is a semiconductor device having a test pattern located at a lower level than the metal wiring.
  10. In paragraph 1, The above gate structure is a semiconductor device having a test pattern that does not overlap with the active region.
  11. In paragraph 1, The above gate structure is a semiconductor device having a test pattern that does not overlap with the metal wiring contact.
  12. In paragraph 1, The above gate structure is a semiconductor device having a test pattern that partially overlaps with the metal wiring.
  13. In paragraph 3, The semiconductor device having a test pattern that electrically connects the third and fourth nodes through the metal wiring, the metal wiring contact, and the active region.
  14. In paragraph 1, The above active region has a long axis and a short axis, and The above gate structure includes a zigzag shape, A semiconductor device having a test pattern in which the length extended in the short axis direction of the active region is greater than the length extended in the long axis direction of the active region.
  15. delete
  16. A step of providing a substrate having a plurality of active regions defined by a device isolation layer and spaced apart at a certain interval and aligned; A step of forming a gate structure on the device isolation layer between the adjacent active regions; A step of forming a pair of metal wiring contacts on the above active regions; and A step of forming metal wiring connecting the metal wiring contacts facing each other in adjacent active regions. Includes, The above active regions are It is composed of an island shape having a major axis and a minor axis, and is aligned at regular intervals in the major axis direction and the minor axis direction, and The above gate structure includes a zigzag shape, A method for manufacturing a semiconductor device having a test pattern in which the length extended in the long axis direction of the active region is greater than the length extended in the short axis direction of the active region.
  17. In Paragraph 16, The step of forming the above gate structure is, A step of sequentially stacking an insulating material layer, an electrode material layer, and a hard mask layer on the above substrate; and Step of etching the hard mask layer, electrode material layer, and insulating material layer in sequence to form a gate structure that does not overlap with the active regions. A method for manufacturing a semiconductor device having a test pattern including
  18. In Paragraph 16, After the step of forming the above gate structure, A method for manufacturing a semiconductor device having a test pattern, further comprising the step of forming doping regions by injecting impurities into the active regions.
  19. In Paragraph 18, A method for manufacturing a semiconductor device having a test pattern including the above impurities, such as N-type impurities or P-type impurities.
  20. In Paragraph 16, The step of forming the above metal wiring contact is, A step of forming an interlayer insulating layer on a substrate including the above gate structure; A step of forming a contact hole that penetrates the interlayer insulation layer to expose the active region; and Step of forming a metal wiring contact that fills the above contact hole A method for manufacturing a semiconductor device having a test pattern including

Description

Semiconductor device equipped with a test pattern and method for manufacturing the same The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device having a test pattern and a method for manufacturing the same. As semiconductor devices become more highly integrated, the driving speed of the semiconductor device is becoming important. The driving speed of a semiconductor device is determined by the threshold voltage (hereinafter referred to as VT), and the factor that has the greatest influence on VT is the gate linewidth, which determines the channel length of the gate. Therefore, measuring the gate linewidth is a very important factor in understanding device characteristics. FIGS. 1a to 1c are drawings showing a semiconductor device having a test pattern according to an embodiment. FIGS. 2a to 2i are examples of a method for manufacturing a semiconductor device having a test pattern according to one embodiment. FIGS. 3a to 3i are cross-sectional views along A-A' of FIGS. 2a to 2i. FIGS. 4a and 4b are top views of a semiconductor device having a test pattern according to one embodiment. The embodiments described herein will be explained with reference to cross-sectional views, plan views, and block drawings, which are ideal schematic diagrams of the invention. Accordingly, the shapes of the exemplary drawings may be modified due to manufacturing techniques and/or tolerances, etc. Therefore, the embodiments of the invention are not limited to the specific shapes depicted but include variations in shape resulting from the manufacturing process. Accordingly, the regions illustrated in the drawings have schematic properties, and the shapes of the regions illustrated in the drawings are intended to illustrate specific forms of the regions of the device and are not intended to limit the scope of the invention. FIGS. 1a to 1c are drawings showing a semiconductor device having a test pattern according to an embodiment. FIG. 1a is a top-view showing a semiconductor device having a test pattern according to an embodiment. FIG. 1b is a cross-sectional view along A-A' of FIG. 1a. FIG. 1c is a cross-sectional view along B-B' of FIG. 1a, but with redundant components omitted for the sake of explanation. First, as illustrated in FIG. 1a, the test pattern (100) of the semiconductor device may include an active region (111), a metal wiring contact (113), a metal wiring (114), and a gate structure (DG). The test pattern (100) of the semiconductor device may include a first node (NA) and a second node (NB) for measuring the line width of the gate. The test pattern (100) of the semiconductor device may include a third node (NC) and a fourth node (ND) for measuring the metal wiring contact resistance. The active region (111) can be defined by a device isolation layer (103, see FIG. 1b). The active region (111) can be formed in an island shape having a major axis and a minor axis. Multiple active regions (111) can be formed. Multiple active regions (111) can all have the same size and shape. The active regions (111) can be aligned at regular intervals. The active regions (111) can be aligned at regular intervals in the major axis direction and the minor axis direction. The active region (111) may be a doped region doped with N-type or P-type impurities. The active region (111) may serve to connect the lower part of the metal wiring contact (113). The active region (111) is for measuring the metal wiring contact resistance, and at least 500 or more may be formed. The active region (111) may additionally form a dummy active region to protect the internal active regions (111) at the edges of the active regions used for measuring contact resistance. The dummy active region may not be doped with impurities. A gate structure (DG) may be formed so as not to overlap with an active region (111). That is, the gate structure (DG) may be formed on a device isolation layer (103, see FIG. 1b) between adjacent active regions (111). The gate structure (DG) may include a gate pattern. The gate structure (DG) may include a bar shape. That is, the gate pattern may include a bar shape. The gate structure (DG) may include a bar shape extending in the short-axis direction of the active region (111). A first node (NA) and a second node (NB) may be included on both ends of the gate structure (DG). The linewidth of the gate structure (DG) can be determined by measuring the resistance of the gate structure (DG) through the first node (NA) and the second node (NB). The gate structure (DG) can be formed as a gate structure (DG) having the same linewidth as the gate of an NMOS, or as a gate structure (DG) having the same linewidth as the gate of a PMOS. That is, the linewidth of the gate structure (DG) can be formed as the same linewidth as the gate formed in the area to be measured, and can be adjusted, for example, from 10 nm to 1000 nm. A dummy gate structure may be for