KR-102963668-B1 - METHOD OF FORMING A WIRING STRUCTURE, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME, AND SEMICONDUCOTR DEVICE MANUFACTURED BY THE SAME METHOD

KR102963668B1KR 102963668 B1KR102963668 B1KR 102963668B1KR-102963668-B1

Abstract

In a method for forming a wiring structure, an electrode film containing graphene and an insulating film containing hexagonal boron nitride (h-BN) can be alternately and repeatedly stacked on a substrate. By performing a first dry etching process using a fluorine-containing etching gas to etch the first insulating film formed on the uppermost layer among the insulating films, an opening can be formed to expose the upper surface of the first electrode film formed on the uppermost layer among the electrode films. By performing a reactive ion etching (RIE) process using oxygen plasma and/or hydrogen plasma to remove the exposed portion of the first electrode film, the opening can be expanded to expose the upper surface of a second insulating film formed below the first electrode film among the insulating films. By performing a second dry etching process using a fluorine-containing etching gas to etch the exposed second insulating film, the opening can be expanded to expose the upper surface of a second electrode film formed below the second insulating film among the electrode films. A contact plug can be formed within the expanded opening.

Inventors

김민식
이관형
김석훈
신용준

Assignees

삼성전자주식회사
서울대학교산학협력단

Dates

Publication Date: 20260512
Application Date: 20220726
Priority Date: 20220531

Claims (10)

On a substrate, an electrode film containing graphene and an insulating film containing hexagonal boron nitride (h-BN) are alternately and repeatedly stacked; By performing a first dry etching process using a fluorine-containing etching gas to etch the first insulating film formed on the uppermost layer among the insulating films, an opening is formed to expose the upper surface of the first electrode film formed on the uppermost layer among the electrode films; By performing a reactive ion etching (RIE) process using oxygen plasma and/or hydrogen plasma to remove the exposed portion of the first electrode film, the opening is expanded to expose the upper surface of the second insulating film formed below the first electrode film among the insulating films; By performing a second dry etching process using a fluorine-containing etching gas to etch the exposed second insulating film, the opening is expanded to expose the upper surface of the second electrode film formed below the second insulating film among the electrode films; and It includes forming a contact plug within the expanded opening, A method for forming a wiring structure in which, by performing the first dry etching process, a fluorine component contained in the etching gas combines with the first electrode film to form graphene fluoride.
A method for forming a wiring structure according to claim 1, wherein the fluorine-containing etching gas comprises xenon difluoride ( XeF₂ ), carbon tetrafluoride ( CF₄ ), or sulfur hexafluoride ( SF₆ ).
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A method for forming a wiring structure according to claim 1, wherein the first electrode film acts as an etching stop film in the first dry etching process.
A method for forming a wiring structure according to claim 1, wherein the second insulating film is not removed when the first dry etching process is performed.
A first channel is formed on a substrate; First source/drain electrodes comprising graphene are formed on the substrate, each covering both sides of the first channel; A first insulating film covering the first channel and the first source/drain electrodes is formed on the substrate; A gate electrode containing graphene is formed on the first insulating film; A second insulating film covering the gate electrode is formed on the first insulating film; A second channel is formed on the second insulating film; Second source/drain electrodes comprising graphene are formed on the second insulating film, each covering both sides of the second channel; A third insulating film covering the second channel and the second source/drain electrodes is formed on the second insulating film; A first contact plug is formed that penetrates the third insulating film and contacts the upper surface of the second source/drain electrode formed on the first side of the second channel; A second contact plug is formed that penetrates the first to third insulating films and contacts the upper surface of the first source/drain electrode formed on the first side of the first channel; A third contact plug is formed that penetrates the first to third insulating films and the second source/drain electrode formed on the second side of the second channel, and contacts the upper surface of the first source/drain electrode formed on the second side of the first channel; and A method for manufacturing a semiconductor device comprising forming a fourth contact plug that penetrates the second and third insulating films and contacts the upper surface of the gate electrode.
In claim 6, forming the second contact plug is, By performing a dry etching process using a fluorine-containing etching gas to etch the first to third insulating films, an opening is formed that exposes the upper surface of the first source/drain electrode formed on the first side of the first channel; and A method for manufacturing a semiconductor device comprising forming a second contact plug that fills the opening.
In claim 6, forming the third contact plug is, By performing a first dry etching process using a fluorine-containing etching gas to etch the third insulating film, an opening is formed that exposes the upper surface of the second source/drain electrode formed on the second side of the second channel; By performing a reactive ion etching (RIE) process using oxygen plasma and/or hydrogen plasma to remove the exposed second source/drain electrode portion, the opening is expanded to expose the upper surface of the second insulating film; By performing a second dry etching process using a fluorine-containing etching gas to etch the first and second insulating films, the opening is expanded to expose the upper surface of the first source/drain electrode formed on the second side of the first channel; and A method for manufacturing a semiconductor device comprising forming a third contact plug that fills the expanded opening.
A method for manufacturing a semiconductor device according to claim 8, wherein, by performing the first and second dry etching processes, a fluorine component contained in the etching gas combines with the second source/drain electrode and the first source/drain electrode, respectively, to form graphene fluoride.
A first insulating film formed on a substrate; A first channel formed on the first insulating film; First source/drain electrodes comprising graphene, each in contact with the upper surfaces of the two sides of the first channel and the adjacent first insulating film portions; A second insulating film formed on the first insulating film, covering the first channel and the first source/drain electrodes; A gate electrode formed on the second insulating film and comprising graphene; A third insulating film formed on the second insulating film covering the gate electrode; A second channel formed on the third insulating film above; Second source/drain electrodes comprising graphene, each in contact with the upper surfaces of the two sides of the second channel and the adjacent third insulating film portions; A fourth insulating film formed on the third insulating film, covering the second channel and the second source/drain electrodes; A first contact plug that penetrates the fourth insulating film and contacts the upper surface of the second source/drain electrode formed on the first side of the second channel; A second contact plug that penetrates the second to fourth insulating films and contacts the upper surface of the first source/drain electrode formed on the first side of the first channel; A third contact plug that penetrates the second to fourth insulating films and the second source/drain electrode formed on the second side of the second channel, and contacts the upper surface of the first source/drain electrode formed on the second side of the first channel; and A semiconductor device comprising a fourth contact plug that penetrates the third and fourth insulating films and contacts the upper surface of the gate electrode.

Description

Method of forming a wiring structure, method of manufacturing a semiconductor device using the same, and semiconductor device manufactured through the same The present invention relates to a method for forming a wiring structure, a method for manufacturing a semiconductor device using the same, and a semiconductor device manufactured through the same. While silicon-containing channels are generally used in semiconductor devices, limitations in the electrical characteristics of silicon-containing channels are becoming apparent as these devices become miniaturized. Accordingly, channels containing two-dimensional materials with higher charge mobility characteristics compared to silicon are being developed, and electrodes containing graphene, a representative two-dimensional material, are also being developed. However, further research is required for graphene-containing electrodes to be used as part of actual semiconductor devices. FIGS. 1 to 5 are cross-sectional views illustrating a method for forming a wiring structure according to exemplary embodiments. FIGS. 6 to 23 are plan and cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. [Example] FIGS. 1 to 5 are cross-sectional views illustrating a method for forming a wiring structure according to exemplary embodiments. Referring to FIG. 1, an insulating film (110) and an electrode film (120) can be alternately and repeatedly stacked on a substrate (100), and then a first mask (130) can be formed on the top insulating film (110). In the drawings, for example, three insulating films (110) and two electrode films (120) are shown alternately stacked on a substrate (100), but the concept of the present invention is not limited thereto, and each insulating film (110) and electrode film (120) may be formed on any number of layers. The substrate (100) may include, for example, a semiconductor material such as silicon, germanium, silicon-germanium, etc., or an insulating material such as, for example, silicon oxide. The insulating film (110) may include, for example, hexagonal boron nitride (h-BN), silicon oxide, silicon nitride, etc. The electrode film (120) may include, for example, graphene. The first mask (130) may include, for example, polymethyl methacrylate (PMMA), photoresist pattern, etc. Referring to FIG. 2, a first dry etching process using a first mask (130) as an etching mask can be performed to etch the top layer insulating film (110), thereby forming a first opening (140) that exposes the upper surface of the upper layer electrode film (120). At this time, the top layer insulating film (110) can be patterned to form an insulating pattern (115). In exemplary embodiments, the first dry etching process may be performed using an etching gas containing fluorine (F), such as xenon difluoride ( XeF₂ ), carbon tetrafluoride ( CF₄ ), sulfur hexafluoride ( SF₆ ), etc. Accordingly, the upper surface of the upper electrode film (120) exposed through the first dry etching process may be fluorinated to form fluorinated graphene, which may act as a kind of etching stop layer in the first dry etching process. Therefore, during the first dry etching process, the upper surface of the insulating film (110) formed below the upper electrode film (120) may not be removed. Referring to FIG. 3a, for example, after removing the first mask (130) by performing an ashing process and/or a stripping process, a first conductive film filling the first opening (140) is formed on the upper surface of the exposed upper electrode film (120) and the upper surface of the insulating pattern (115), and a flattening process can be performed on the first conductive film until the upper surface of the insulating pattern (115) is exposed. Accordingly, a first contact plug (150) that contacts the upper surface of the upper electrode film (120) can be formed within the first opening (140). The above planarization process may include, for example, a chemical mechanical polishing (CMP) process and/or an etch back process. The first conductive film may include, for example, a metal such as copper, aluminum, ruthenium, titanium, tantalum, chromium, palladium, etc. In contrast, referring to FIG. 3b, the exposed upper electrode film (120) portion can be removed by, for example, performing a reactive ion etching (RIE) process, and thus an electrode (125) can be formed. The above RIE process can be performed using, for example, oxygen plasma, hydrogen plasma, etc. Below, we will further describe the case where an electrode (125) is formed by performing the process described with reference to FIG. 3b. Referring to FIG. 4, processes substantially identical or similar to those described with reference to FIG. 2 can be performed. That is, the insulating film (110) formed in the middle layer can be etched by