KR-102963697-B1 - CASTELLATION, HATCHING, AND OTHER SURFACE PATTERNS IN DIELECTRIC SURFACES FOR BONDING WITH INCREASED SURFACE AREA, BOND STRENGTH, AND ALIGNMENT

Abstract

A semiconductor device comprises a semiconductor substrate having a first main surface and a second main surface facing the first main surface, a first layer of dielectric material on the first main surface, and a second layer of dielectric material on the second main surface. The first layer comprises a plurality of recesses, and the second layer comprises a plurality of protrusions. Each of the plurality of recesses is defined by a shape, and each of the plurality of protrusions is aligned perpendicularly with a corresponding recess among the plurality of recesses and is defined by the shape of a corresponding recess among the plurality of recesses.

Inventors

• 커비, 카일 케이.

Assignees

• 마이크론 테크놀로지, 인크

Dates

Publication Date

20260512

Application Date

20220825

Priority Date

20220705

Claims (20)

1. In semiconductor devices, A semiconductor substrate having a first main surface and a second main surface facing the first main surface; A first layer of dielectric material on the first main surface above - said first layer comprises a plurality of recesses, each of said plurality of recesses is defined by its shape - ; and A second layer of dielectric material on the second main surface—the second layer comprises a plurality of tapered protrusions, each of which is aligned perpendicularly with a corresponding recess among the plurality of recesses and is defined by the shape of a corresponding recess among the plurality of recesses—and The plurality of protrusions are included in the vertical rows and columns of protrusions located along the periphery of the second main surface, and also The above vertical rows and columns include at least two rows or at least two columns along each side of the periphery of the second main surface, and A semiconductor device comprising at least one of the plurality of recesses having a first conductive contact disposed therein, and at least one of the plurality of protrusions having a corresponding second conductive contact disposed thereon.
2. delete
3. A semiconductor device according to claim 1, wherein at least one of the plurality of recesses comprises a first dual damascene pad, and at least one of the plurality of protrusions comprises a second dual damascene pad.
4. A semiconductor device according to claim 1, wherein at least one of the plurality of recesses includes a first conductive via, and at least one of the plurality of protrusions includes a second conductive via.
5. A semiconductor device according to claim 1, wherein each of the plurality of recesses comprises a flat bottom surface.
6. A semiconductor device according to claim 1, wherein each of the plurality of protrusions comprises a flat top surface.
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8. A semiconductor device according to claim 1, wherein the dielectric material comprises tetraethyl orthosilicate, silicon carbonitride, silicon dioxide, or a combination thereof.
9. In semiconductor devices, As a first semiconductor die, A first semiconductor substrate having a first main surface, and The first semiconductor die comprising a first layer of dielectric material on the first main surface—the first layer comprises a plurality of recesses, each of the plurality of recesses being defined by its shape—and As a second semiconductor die, A second semiconductor substrate having a second main surface facing the first main surface, and The second semiconductor die comprises a second layer of dielectric material on the second main surface, wherein the second layer comprises a plurality of tapered protrusions, each of which is aligned perpendicularly with a corresponding recess among the plurality of recesses and is defined by the shape of a corresponding recess among the plurality of recesses. The plurality of protrusions are included in the vertical rows and columns of protrusions located along the periphery of the second main surface, and also The above vertical rows and columns include at least two rows or at least two columns along each side of the periphery of the second main surface, and A semiconductor device comprising at least one of the plurality of recesses having a first conductive contact disposed therein, and at least one of the plurality of protrusions having a corresponding second conductive contact disposed thereon.
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11. A semiconductor device according to claim 9, wherein at least one of the plurality of recesses comprises a first dual damascene pad, and at least one of the plurality of protrusions comprises a second dual damascene pad.
12. A semiconductor device according to claim 9, wherein each of the plurality of recesses comprises a first surface and first sidewalls, and each of the plurality of protrusions comprises a second surface and second sidewalls having the same dimensions as the first surface and first sidewalls.
13. A semiconductor device according to claim 12, wherein the first sidewalls are configured to form an angle and the second sidewalls are configured at the same angle as the first sidewalls.
14. A semiconductor device according to claim 13, wherein the angle is greater than 0 degrees and less than 90 degrees.
15. A semiconductor device according to claim 9, wherein the first layer of the dielectric material comprises the same material as the second layer of the dielectric material.
16. A method for forming a semiconductor device, wherein the method comprises: As a step of forming a first semiconductor die, The step of providing a first semiconductor substrate having a first main surface, and A step of forming the first semiconductor die, comprising the step of providing a first layer of dielectric material on the first main surface; A step of forming a plurality of recesses in the first layer above - each of the plurality of recesses is defined by its shape -; As a step of forming a second semiconductor die, The step of providing a second semiconductor substrate having a second main surface, and A step of forming the second semiconductor die, comprising the step of providing a second layer of dielectric material on the second main surface; A step of forming a plurality of tapered protrusions on the second layer—each of the plurality of protrusions is defined by a corresponding shape among the plurality of recesses, and the plurality of protrusions are included in vertical rows and columns of protrusions arranged along the periphery of the second main surface, and the vertical rows and columns also include at least two rows or at least two columns along each side of the periphery of the second main surface—; and The method includes the step of aligning each of the plurality of protrusions with the corresponding one among the plurality of recesses. A method further comprising the step of providing a first conductive contact on a first layer of the dielectric material and a second conductive contact on a second layer of the dielectric material.
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18. In Paragraph 16, A method further comprising the step of electrically coupling the first conductive contact with the second conductive contact.
19. In claim 16, the step of forming the recesses comprises the step of etching the material from the first layer of the dielectric material.
20. In claim 16, the step of forming the protrusions comprises the step of etching the material from the second layer of the dielectric material.

Description

Castellation, hatching, and other surface patterns in dielectric surfaces for bonding with increased surface area, bond strength, and alignment Cross-reference regarding related applications This application claims priority to U.S. Provisional Application No. 63/238,071 filed on August 27, 2021, the entire disclosure of which is incorporated herein by reference. Technology field The present invention generally relates to semiconductor devices having surface patterns on dielectric surfaces, and more specifically, to semiconductor devices having surface patterns for increasing the surface area, bond strength, and alignment of hybrid and fusion bonding of semiconductor die stacks. Semiconductor device manufacturers often seek to manufacture smaller, faster, and/or more powerful devices with higher-density components for computers, cell phones, pagers, personal digital assistants, and many other products. Die manufacturers are under pressure to increase the capacity of the resulting encapsulated assembly while reducing the volume occupied by the die. To meet these demands, die manufacturers often stack multiple dies on top of each other to increase the capacity or performance of the device within a limited surface area on the circuit board or other element on which the dies are mounted. Stacked semiconductor devices, such as three-dimensional integrated circuits (3DICs), generally enjoy a reduced footprint compared to conventional arrangements. Fusion and hybrid bonding are bonding procedures for forming 3DICs. In fusion bonding, dielectric bonds are formed between the dielectric layers of two opposing semiconductor dies. Hybrid bonding further involves metal-metal bonds formed between the conductive structures of the dies. Hybrid bonding shows great potential for forming assemblies with reduced height and better thermal performance; therefore, improved approaches to hybrid bonding are greatly required. Many aspects of the present technology can be better understood by referring to the following drawings. The components of the drawings are not required to be scaled. Instead, emphasis is placed on clearly illustrating the principles of the present technology. FIG. 1a is a cross-sectional view of a semiconductor device having protrusions and recesses according to one embodiment of the present technology, FIG. 1b is an enlarged cross-sectional view of the semiconductor device of FIG. 1a, and FIG. 1c is a bottom view of the semiconductor device of FIG. 1a. FIGS. 2a and 2b are cross-sectional views of another semiconductor device including a plurality of protrusions and recesses according to one embodiment of the present technology. FIGS. 2c and 2d are enlarged cross-sectional views of a semiconductor device having protrusions and recesses according to embodiments of the present technology. FIG. 3 is a cross-sectional view of a semiconductor die having a plurality of recesses and protrusions according to one embodiment of the present technology. FIG. 4a is a cross-sectional view of a semiconductor device having a plurality of recesses and protrusions according to one embodiment of the present technology, and FIG. 4b is a bottom view of the semiconductor device of FIG. 4a. FIG. 5 is a cross-sectional view of a semiconductor die having a plurality of recesses and protrusions according to one embodiment of the present technology. FIG. 6a is a cross-sectional view of a semiconductor device before assembly according to one embodiment of the present technology, and FIG. 6b is a cross-sectional view of the semiconductor device of FIG. 6a after assembly. FIG. 7 is a flowchart of a method for forming a semiconductor device according to one embodiment of the present technology. FIG. 8 is a schematic diagram of a system including a semiconductor assembly configured according to embodiments of the present technology. Specific details of some embodiments of semiconductor devices having surface patterns on dielectric surfaces to improve fusion and hybrid bonding are disclosed. In some embodiments, for example, the semiconductor device comprises a semiconductor substrate having a first major surface and a second major surface facing the first major surface. The semiconductor device may also comprise a first layer of dielectric material on the first major surface. The first layer may comprise a plurality of recesses, each of which may be defined by a shape. The semiconductor device may further comprise a second layer of dielectric material on the second major surface. The second layer may comprise a plurality of protrusions. Each of the plurality of protrusions may be aligned perpendicularly with a corresponding one of the plurality of recesses and may be defined by a shape of a corresponding one of the plurality of recesses. The present technology can increase the surface area, bond strength, and alignment during fusion and hybrid bonding of the semiconductor device. Those skilled in the art will recognize that, unless the context