KR-102963948-B1 - INTEGRATED CIRCUIT INCLUDING CELL ARRAY WITH WORD LINE ASSIST CELLS

Abstract

The integrated circuit may include a cell array comprising a plurality of memory cells in a plurality of first columns and a plurality of word line auxiliary cells in at least one second column, a plurality of word lines each extending over a plurality of first rows of the cell array and connected to the plurality of memory cells and the plurality of word line auxiliary cells, and a row driver configured to drive the plurality of word lines, wherein each of the word line auxiliary cells is configured to accelerate the activation of the word line, includes transistors identical to each of the plurality of memory cells, and may have a footprint identical to each of the plurality of memory cells.

Inventors

• 최태민
• 정성욱
• 조건희

Assignees

• 삼성전자주식회사
• 연세대학교 산학협력단

Dates

Publication Date

20260511

Application Date

20201030

Claims (20)

1. A cell array comprising a plurality of memory cells in a plurality of first columns and a plurality of word line auxiliary cells in at least one second column; A plurality of word lines each extending over a plurality of first rows of the cell array and connected to the plurality of memory cells and the plurality of word line auxiliary cells; At least one pseudo-bit line each extending over the at least one second column and including a first pseudo-bit line; and It includes a row driver configured to drive the plurality of word lines mentioned above, and Each of the plurality of word line auxiliary cells is configured to accelerate the activation of a word line based on the voltage of at least one pseudo-bit line, includes transistors identical to each of the plurality of memory cells, and has a footprint identical to each of the plurality of memory cells. Each of the above plurality of word line auxiliary cells is, A first PFET (p-channel field effect transistor) connected between a first power node and a first node, and including a control terminal connected to a first word line; A first NFET (n-channel field effect transistor) connected between the first node and the first pseudo-bit line and including a control terminal connected to the first word line; and An integrated circuit characterized by including a second PFET connected between the first power node and the first word line, and including a control terminal connected to the first node.
2. delete
3. In claim 1, An integrated circuit further comprising a column driver configured to apply a negative supply voltage to the first pseudo-bit line before the first word line is activated, and to apply a positive supply voltage to the first pseudo-bit line before the activated first word line is deactivated.
4. In claim 1, At least one power line extending on each of the above at least one second column; and An integrated circuit further comprising a column driver connected to the first power node through a first power line, configured to apply a positive supply voltage to the first power line before the first word line is activated, and to float the first power line before the activated first word line is deactivated.
5. In claim 1, The above at least one pseudo-bit line further includes a second pseudo-bit line, and Each of the above plurality of word line auxiliary cells is, A second NFET connected between a second node and a second power node to which a negative supply voltage is applied, and comprising a control terminal connected to the first node; A third NFET connected between the first node and the first pseudo-bit line and including a control terminal connected to the first word line; and An integrated circuit characterized by including a fourth NFET connected between the second pseudo-bit line and the second node, and including a control terminal connected to the first word line.
6. In claim 1, The above cell array is, A plurality of entry auxiliary cells in at least one second row; and In the area where the above at least one second column and the above at least one second row intersect, at least one dummy cell is further included, An integrated circuit characterized in that each of the plurality of write assist cells and each of the at least one dummy cell includes transistors identical to each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.
7. In claim 6, The cell array further includes a plurality of first dummy cells each disposed adjacently in the row direction or column direction to each of the plurality of writing auxiliary cells in the at least one second row, and The above at least one dummy cell is, A dummy cell corresponding to the same circuit as each of the plurality of first dummy cells above; and An integrated circuit characterized by including a second dummy cell corresponding to a different circuit from each of the plurality of first dummy cells.
8. In claim 7, The above at least one pseudo-bit line further includes a second pseudo-bit line, and The above second dummy cell is, A third PFET and a fourth PFET, each including control terminals connected to the first pseudo-bit line and floating current terminals; A fifth NFET and a sixth NFET including control terminals connected to the first pseudo-bit line; A seventh NFET connected between the first pseudo-bit line and the fifth NFET, and including a control terminal connected to the first pseudo-bit line; and An integrated circuit characterized by including an 8th NFET connected between the 2nd pseudo-bit line and the 6th NFET and connected to the 1st pseudo-bit line.
9. As an integrated circuit, A cell array comprising a plurality of cells, each including identical transistors and each having the same footprint; A plurality of word lines each extending on a plurality of first rows of the cell array; and It includes a row driver connected to the plurality of word lines above, and The above plurality of cells are, A plurality of memory cells connected to the above plurality of word lines and arranged in a series of first columns; A plurality of first word line auxiliary cells connected to the plurality of word lines and arranged in a second column; and It includes a plurality of second word line auxiliary cells connected to the plurality of word lines and disposed in a third column adjacent to the second column, and Each of the above plurality of first word line auxiliary cells has a first layout in which a second layout of a second word line auxiliary cell placed in the same row is flipped about an axis parallel to the column direction, and The above integrated circuit is, It further includes a first pseudo-bit line and a second pseudo-bit line extending on the second column and connected to the plurality of first word line auxiliary cells, and Each of the above plurality of first word line auxiliary cells is, A first PFET (p-channel field effect transistor) connected between a first power node and a first node, and including a control terminal connected to a first word line; A first NFET (n-channel field effect transistor) connected between the first node and the first pseudo-bit line and including a control terminal connected to the first word line; and An integrated circuit characterized by including a second PFET connected between the first power node and the first word line, and including a control terminal connected to the first node.
10. In claim 9, The above plurality of memory cells each have a plurality of mutually flipped layouts, An integrated circuit characterized in that each of the first layout and the second layout comprises active regions and gate electrodes identical to one of the plurality of layouts.
11. In claim 10, The above active regions extend in the column direction, and An integrated circuit characterized in that the gate electrodes extend in the row direction.
12. In claim 9, A plurality of bit lines each extending over the above series of first columns and connected to the plurality of memory cells; A third pseudo-bit line and a fourth pseudo-bit line extending on the third column and connected to the plurality of second word line auxiliary cells; and The column driver connected to the plurality of bit lines, the second pseudo-bit line, and the third pseudo-bit line is further included. An integrated circuit characterized in that the first pseudo-bit line and the fourth pseudo-bit line are configured to have a negative supply voltage applied.
13. In claim 12, An integrated circuit further comprising a plurality of patterns connecting the second pseudo-bit line and the third pseudo-bit line on the cell array.
14. In claim 13, An integrated circuit characterized in that the above plurality of patterns are formed in a wiring layer on which the first to fourth pseudo-bit lines are formed.
15. In claim 9, A first power line extending on the second column and connected to the plurality of first word line auxiliary cells; A second power line extending on the third column and connected to the plurality of second word line auxiliary cells; and An integrated circuit further comprising a column driver configured to selectively provide a positive supply voltage to the plurality of first word line auxiliary cells through the first power line and to selectively provide a positive supply voltage to the plurality of second word line auxiliary cells through the second power line.
16. In claim 9, The above plurality of cells are, A plurality of writing auxiliary cells disposed in at least one second row of the cell array; and An integrated circuit further comprising a plurality of dummy cells disposed in an area where at least one second row intersects the second column and the third column.
17. In claim 16, An integrated circuit characterized in that the plurality of dummy cells include a first dummy cell and a second dummy cell, each corresponding to different circuits, which are respectively arranged in the second column and the third column in the second row.
18. As an integrated circuit, A cell array comprising a plurality of cells, each including identical transistors and each having the same footprint; A plurality of word lines each extending on a plurality of first rows of the cell array; and It includes a row driver connected to the plurality of word lines above, and The above plurality of cells are, A plurality of first memory cells connected to the plurality of word lines and arranged in a series of first columns; A plurality of first word line auxiliary cells connected to the plurality of word lines and disposed in at least one second column adjacent to the series of first columns; and It includes a plurality of second memory cells connected to the plurality of word lines and arranged in a series of third columns adjacent to the at least one second column, The above integrated circuit is, It further includes at least one first pseudo-bit line that is extended on each of the above-mentioned at least one second column and connected to the plurality of first word line auxiliary cells, and Each of the above plurality of first word line auxiliary cells is, A first PFET (p-channel field effect transistor) connected between a first power node and a first node, and including a control terminal connected to a first word line; A first NFET (n-channel field effect transistor) connected between the first node and the first pseudo-bit line and including a control terminal connected to the first word line; and An integrated circuit comprising a second PFET connected between the first power node and the first word line, and including a control terminal connected to the first node.
19. In claim 18, It further includes a plurality of second word line auxiliary cells connected to the plurality of word lines and disposed in at least one fourth column adjacent to the series of third columns, and An integrated circuit characterized in that the number of the first columns in the above series and the number of the third columns in the above series are the same.
20. In claim 19, A plurality of bit lines extending respectively over the series of first columns and the series of third columns and connected to the plurality of first memory cells and the plurality of second memory cells; At least one second pseudo-bit line each extending on the at least one fourth column and connected to the plurality of second word line auxiliary cells; and An integrated circuit further comprising a column driver connected to the plurality of bit lines and configured to enable or disable the plurality of first word line auxiliary cells and the plurality of second word line auxiliary cells through the at least one first pseudo-bit line and the at least one second pseudo-bit line.

Description

Integrated circuit including a cell array with word line assist cells The technical concept of the present disclosure relates to an integrated circuit, and more specifically, to an integrated circuit comprising a cell array having a word line auxiliary cell. Due to the demand for high integration density and advancements in semiconductor processes, the width, spacing, and/or height of wiring included in integrated circuits may decrease, and parasitic elements in the wiring may increase. Furthermore, to achieve reduced power consumption and higher operating speeds, the power supply voltage of the integrated circuit may be lowered; consequently, the impact of parasitic elements in the wiring on the integrated circuit may become more significant. Despite these parasitic elements, integrated circuits containing cell arrays composed of memory cells may be required to reliably provide high performance according to the requirements of various applications. FIG. 1 is a block diagram showing an integrated circuit according to an exemplary embodiment of the present disclosure. FIG. 2 is a plan view showing the layout of a cell array according to an exemplary embodiment of the present disclosure. FIG. 3 is a circuit diagram showing an example of a memory cell and a word line auxiliary cell according to an exemplary embodiment of the present disclosure. FIG. 4 is a timing diagram showing a reading operation according to an exemplary embodiment of the present disclosure. FIG. 5 is a circuit diagram showing an example of a memory and a word line auxiliary cell according to an exemplary embodiment of the present disclosure. FIG. 6 is a timing diagram showing a reading operation according to an exemplary embodiment of the present disclosure. FIG. 7 is a plan view showing the layout of a cell array according to an exemplary embodiment of the present disclosure. FIG. 8 is a plan view showing the layout of a cell array according to an exemplary embodiment of the present disclosure. FIG. 9 is a block diagram showing an integrated circuit according to an exemplary embodiment of the present disclosure. FIG. 10 is a plan view showing the layout of a cell array according to an exemplary embodiment of the present disclosure. FIG. 11 is a circuit diagram showing examples of a memory cell, a word line auxiliary cell, a write auxiliary cell, and a dummy cell according to an exemplary embodiment of the present disclosure. FIG. 12 is a plan view showing the layout of a cell array according to an exemplary embodiment of the present disclosure. FIGS. 13a and FIGS. 13b are plan views showing the layout of an integrated circuit according to exemplary embodiments of the present disclosure. FIG. 14 is a block diagram showing an integrated circuit according to an exemplary embodiment of the present disclosure. FIG. 15 is a flowchart illustrating a method of operation of an integrated circuit according to an exemplary embodiment of the present disclosure. FIG. 16 is a flowchart illustrating a method of operation of an integrated circuit according to an exemplary embodiment of the present disclosure. FIG. 17 is a flowchart illustrating a method of operation of an integrated circuit according to an exemplary embodiment of the present disclosure. FIG. 18 is a block diagram showing a system-on-chip according to an exemplary embodiment of the present disclosure. FIG. 1 is a block diagram illustrating an integrated circuit according to an exemplary embodiment of the present disclosure. Specifically, the block diagram of FIG. 1 illustrates a memory device (10) included in the integrated circuit. In some embodiments, the integrated circuit may store data based on commands and addresses provided from outside the integrated circuit, and the memory device (10) may be a standalone memory device. Also, in some embodiments, the integrated circuit may further include other components for writing data to the memory device (10) or reading data from the memory device (10), as described below with reference to FIG. 18, and the memory device (10) may be an embedded memory device. As illustrated in FIG. 1, the memory device (10) may include a cell array (12), a row driver (14), a column driver (16), and control logic (18). Although not illustrated in FIG. 1, in some embodiments, the memory device (10) may further include an address buffer, a data buffer, a data input/output circuit, an internal voltage generator, etc. The memory device (10) can receive a command (CMD), an address, and data. For example, the memory device (10) can receive a command (CMD) instructing to write (which may be referred to as a write command), an address (which may be referred to as a write address), and data (which may be referred to as write data), and can store the received data in an area of the cell array (12) corresponding to the address. Additionally, the memory device (10) can receive a command (CMD) instructing to read (which may be referred to as a read command) and an address,