KR-102963951-B1 - Semiconductor device and electronic system

KR102963951B1KR 102963951 B1KR102963951 B1KR 102963951B1KR-102963951-B1

Abstract

A transistor included in a semiconductor device of the present invention comprises: a device isolation region provided on a substrate; an active region located within the device isolation region; a gate extending in a second direction on the active region; and source and drain regions each extending in a first direction perpendicular to the second direction within the active regions on both sides of the gate. The source and drain regions include low-concentration source and drain doping regions, comprising first low-concentration source and drain doping regions located within the substrate of a region adjacent to the gate, and second low-concentration source and drain doping regions located within the substrate of a region adjacent to the gate, and high-concentration source and drain doping regions located within the low-concentration source and drain doping regions and having a higher doping concentration than the low-concentration source and drain doping regions. The first length in the second direction of the first low-concentration source and drain doping regions is greater than the second length in the second direction of the second low-concentration source and drain doping regions. The second low-concentration source and drain doping regions are located away from the side edge located on the inner side of the device isolation region in the first direction.

Inventors

백성권
김학선
서재화

Assignees

삼성전자주식회사

Dates

Publication Date: 20260511
Application Date: 20201228

Claims (10)

A peripheral circuit comprising a plurality of transistors provided on a substrate; and It includes a memory cell array controlled by the above peripheral circuit, and Each of the above transistors is, A device isolation region provided on the above substrate; An active region located within the above-mentioned device isolation region; A gate extended in a second direction on the above active region; and It includes source and drain regions respectively extending in a first direction perpendicular to the second direction within the active region on both sides of the gate, and The above source and drain regions are, Low concentration source and drain doping regions including first low concentration source and drain doping regions located within the substrate in a gate-adjacent region and second low concentration source and drain doping regions located within the substrate in a gate-far adjacent region, and high concentration source and drain doping regions located within the low concentration source and drain doping regions and having a higher doping concentration than that of the low concentration source and drain doping regions, wherein The first length in the second direction of the first low-concentration source and drain doping regions is greater than the second length in the second direction of the second low-concentration source and drain doping regions, and A semiconductor device characterized in that the second low-concentration source and drain doping regions are located away in the first direction from the side edge located on the inner side of the device isolation region.
In claim 1, the first low-concentration source and drain doping regions are located at a distance of a first separation distance in the second direction from a first edge located inside the upper and lower sides of the device isolation region in the second direction, and A semiconductor device characterized in that the second low-concentration source and drain doping regions are located at a second separation distance greater than the first separation distance in the second direction from a second edge located inside the upper and lower sides of the device isolation region in the second direction.
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A semiconductor device according to claim 1, characterized in that the high-concentration source and drain doping regions are located surrounded by the first low-concentration source and drain doping regions and the second low-concentration source and drain doping regions.
In claim 1, the second low-concentration source and drain doping regions include a second low-concentration source doping region located in the gate far-contact region on one side of the gate and a second low-concentration drain doping region located in the gate far-contact region on the other side of the gate. The second low-concentration source doping region is located in contact with a second side edge located on the inner side of the device isolation region, and A semiconductor device characterized in that the second low-concentration drain doping region is located away in the first direction from a first side edge located on the inner side of the device isolation region.
A semiconductor device according to claim 1, characterized in that the high-concentration source and drain doping regions have a deeper doping depth than the low-concentration source and drain doping regions within the substrate.
It includes a peripheral circuit comprising a plurality of transistors, and Each of the above transistors is, A gate extending in a second direction on an active region defined by a device isolation region; and It includes source and drain regions respectively extending in a first direction perpendicular to the second direction within the active region on both sides of the gate, and The above source and drain regions are, Low concentration source and drain doping regions including first low concentration source and drain doping regions located in a region adjacent to the gate, and second low concentration source and drain doping regions located in a region far from the gate, and high concentration source and drain doping regions having a higher doping concentration than the low concentration source and drain regions, wherein The first length in the second direction of the first low-concentration source and drain doping regions is greater than the second length in the second direction of the second low-concentration source and drain doping regions, and The second low-concentration source and drain doping regions include a second low-concentration source doping region located in the gate far-contact region on one side of the gate and a second low-concentration drain doping region located in the gate far-contact region on the other side of the gate. The second low-concentration source doping region is located in contact with a second side edge located on the inner side of the device isolation region, and A semiconductor device characterized in that the second low-concentration drain doping region is located away in the first direction from a first side edge located on the inner side of the device isolation region.
A semiconductor device according to claim 7, wherein the first low-concentration source and drain doping regions and the second low-concentration source and drain doping regions are asymmetric structures with respect to the gate with respect to the first direction.
Main board; A semiconductor device on the main board above; and It includes a controller electrically connected to the semiconductor device on the main board, The semiconductor device includes a peripheral circuit comprising a plurality of transistors, and Each of the above transistors is, A gate extending in a second direction on an active region defined by a device isolation region; and It includes source and drain regions respectively extending in a first direction perpendicular to the second direction within the active region on both sides of the gate, and The above source and drain regions are, Low concentration source and drain doping regions including first low concentration source and drain doping regions located in a region adjacent to the gate, and second low concentration source and drain doping regions located in a region far from the gate, and high concentration source and drain doping regions having a higher doping concentration than the low concentration source and drain regions, wherein The first length in the second direction of the first low-concentration source and drain doping regions is greater than the second length in the second direction of the second low-concentration source and drain doping regions, and An electronic system characterized in that the second low-concentration source and drain doping regions are located away in the first direction from the side edge located on the inner side of the device isolation region.
In claim 9, the first low-concentration source and drain doping regions are located at a first separation distance in the second direction from the first edge inside the device isolation region, and An electronic system characterized in that the second low-concentration source and drain doping regions are located at a second separation distance greater than the first separation distance in the second direction from the second edge inside the device isolation region.

Description

Semiconductor device and electronic system including the same The technical concept of the present invention relates to a semiconductor device and an electronic system including the same, and more specifically, to a semiconductor device including a transistor capable of improving breakdown voltage characteristics and current characteristics, and an electronic system including the same. In electronic systems requiring data storage, semiconductor devices capable of storing large amounts of data, such as flash memory devices, are being proposed. Flash memory devices may include transistors, such as high-voltage transistors. A high-voltage transistor may refer to a transistor with a high breakdown voltage. It is necessary for high-voltage transistors to improve current characteristics in addition to breakdown voltage characteristics. FIG. 1 is a block diagram of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 2 is a schematic perspective view of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 3 is a schematic perspective view of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 4 is an equivalent circuit diagram of a memory cell array (MCA) of a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 5 is a schematic plan view of a part of a semiconductor device according to one embodiment of the technical concept of the present invention. FIGS. 6 to 9 are drawings for explaining in detail a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 10 is a drawing for explaining a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 11 is a cross-sectional view for explaining a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 12 is a plan view for explaining a transistor included in a semiconductor device according to one embodiment of the technical concept of the present invention. FIGS. 13 to 15 are cross-sectional views of the semiconductor device of FIG. 12. FIG. 16 is a plan view for explaining a transistor included in a semiconductor device according to one embodiment of the technical concept of the present invention. FIGS. 17 to 19 are cross-sectional views of the semiconductor device of FIG. 16. FIG. 20 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 21 is a schematic diagram showing an electronic system including a semiconductor device of the technical concept of the present invention. FIG. 22 is a schematic perspective view of an electronic system including a semiconductor device according to one embodiment of the technical concept of the present invention. FIG. 23 is a cross-sectional view schematically showing semiconductor packages according to one embodiment of the technical concept of the present invention. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. The following embodiments of the present invention may be implemented as only one, and may also be implemented by combining one or more of the following embodiments. Accordingly, the technical concept of the present invention is not to be interpreted as being limited to a single embodiment. In this specification, the singular form of the components may include the plural form unless the context clearly indicates otherwise. In this specification, the drawings are illustrated in an exaggerated manner to more clearly explain the invention. FIG. 1 is a block diagram of a semiconductor device according to one embodiment of the technical concept of the present invention. Specifically, the semiconductor device (10) may include a memory cell array (20) and a peripheral circuit (30). The memory cell array (20) may be controlled by the peripheral circuit (30). The memory cell array (20) may include a plurality of memory cell blocks (BLK1, BLK2, ..., BLKp). Each of the memory cell blocks (BLK1, BLK2, ..., BLKp) may include a plurality of memory cells. The memory cell blocks (BLK1, BLK2, ..., BLKp) may be connected to the peripheral circuit (30) through a bit line (BL), a word line (WL), a string select line (SSL), and a ground select line (GSL). The peripheral circuit (30) may include a row decoder (32), a page buffer (34), a data input/output circuit (36), control logic (38), and a common source line driver (39). The peripheral circuit (30) may further include various circuits such as a voltage generation circuit that generates various voltages required for the operation of the semiconductor device (10), an error correction circuit for correcting errors in data read from the memory cell array (20), and an inp