Search

KR-102963952-B1 - SEMICONDUCTOR DEVICE INCLUDING TSV TEST DEVICE AND METHOD OF THEREOF

KR102963952B1KR 102963952 B1KR102963952 B1KR 102963952B1KR-102963952-B1

Abstract

A semiconductor device including a TSV test device and a method of operating the same are disclosed. The semiconductor system comprises a buffer die and first to N stack dies stacked on the buffer die and communicating with the buffer die through N (where N is a positive integer) TSVs (Through Silicon Via), wherein N is an integer of 2 or more; and a TSV test device configured to measure voltages at one end and voltages at the other end of the N TSVs respectively according to a clock signal, compare the voltages at one end and the voltages at the other end respectively with a reference voltage, and determine whether each TSV has a plurality of TSV defect types according to the comparison results, wherein the TSV test device can test two or more different TSV defect types for a first TSV included in the N TSVs during one cycle of the clock signal.

Inventors

  • 이영광
  • 강성호

Assignees

  • 삼성전자주식회사
  • 연세대학교 산학협력단

Dates

Publication Date
20260511
Application Date
20210903

Claims (10)

  1. A semiconductor device comprising a buffer die and first to L stack dies stacked on the buffer die and communicating with the buffer die through N (where N is a positive integer) Through Silicon Via (TSVs) (where L is an integer greater than or equal to 2); and A TSV test device configured to measure the voltages at one end and the voltages at the other end of the N TSVs according to a clock signal, compare the voltages at the one end and the voltages at the other end with a reference voltage, and determine whether each TSV has multiple TSV defect types according to the comparison results; The TSV test device tests two or more different TSV defect types for a first TSV included in the N TSVs during one cycle of the clock signal, and A semiconductor system in which the value of the reference voltage for testing the above plurality of TSV defect types is commonly used and set to half of the power supply voltage.
  2. In claim 1, The above plurality of TSV defect types are, A semiconductor system characterized by including, during one cycle of the above clock signal, a first TSV defect type indicating that one of the two ends of the TSV is fixed to the power supply voltage, a second TSV defect type indicating that one of the two ends of the TSV is fixed to the ground voltage, a third TSV defect type indicating that the path between the two ends of the TSV is open, a fourth TSV defect type indicating that the path between the two ends of the TSV is resistively open, a fifth TSV defect type indicating that the TSV is electrically connected to another TSV, and a sixth TSV defect type indicating that current flows out to the substrate due to the breakdown of the insulating film between the TSV and the substrate.
  3. In claim 2, The above TSV test device is, When the above clock signal is 1, the voltage at one end of the first TSV is measured, and Configured to detect that the first TSV is faulty by the first TSV defect type or the fifth TSV defect type when the voltage at one end of the first TSV is greater than or equal to the reference voltage. Semiconductor system.
  4. In claim 3, The above TSV test device is, When the above clock signal is 0, the voltage at one end of the first TSV is measured, and When the voltage of one end of the first TSV is less than the reference voltage, the first TSV is configured to detect that the first TSV is faulty by the second TSV fault type, the third TSV fault type, or the fourth TSV fault type. Semiconductor system.
  5. In claim 4, The above N TSVs include a second TSV spaced apart from the first TSV by an arbitrary distance or more, and The above TSV test device is, A method configured to measure the voltage at the other end of the second TSV when the clock signal is 0, and to detect that the second TSV is faulty by the sixth TSV fault type when the voltage at the other end of the second TSV is less than the reference voltage. Semiconductor system.
  6. In claim 1, The above TSV test device includes M test circuits (where M is an integer greater than or equal to 2) connected in parallel, and The M test circuits test two or more different types of TSV defects for M TSVs, each included one during one cycle of the clock signal. Semiconductor system.
  7. A step of generating an enable signal to determine whether to connect at least one of the power supply voltage or the ground voltage to the first TSV; A step of measuring a first test voltage or a second test voltage divided by a voltage division method based on the voltage applied to the first TSV according to the above enable signal; A step of comparing the first test voltage or the second test voltage with a reference voltage; and The method includes a step of detecting whether the first TSV is faulty based on a comparison result; The failure of the first TSV includes whether it is a first failure corresponding to a bridge defect or a Stuck-at-1 failure, whether it is a second failure corresponding to an open defect, a resistive-open defect, or a Stuck-at-0 failure, or whether it is a third failure corresponding to a pinhole defect. TSV test method.
  8. In claim 7, The reference voltage values for each of the first fault, the second fault, and the third fault are used in common and are set to half of the power supply voltage. TSV test method.
  9. In claim 8, A step of detecting that the first TSV is faulty due to the first fault when the clock signal is 1 and the first test voltage is greater than or equal to the reference voltage; The method further comprises the step of detecting that the first TSV is faulty due to the second fault when the clock signal is 0 and the first test voltage is less than the reference voltage. TSV test method.
  10. In claim 9, The method further comprises the step of detecting that the first TSV is faulty due to the third fault when the second test voltage is less than the reference voltage when the clock signal is 0. TSV test method.

Description

Semiconductor device including TSV test device and method of operation thereof The technical concept of the present disclosure relates to a TSV test device, and more specifically, to a semiconductor device including a test device for detecting failures of a TSV (Through-Silicon-Via) and a method of operating the same. As the amount of data that electronic devices must process increases, there is a demand for high-capacity and high-bandwidth memory devices. To improve the integration density of semiconductor memory, three-dimensional (3D) stacking technology, which stacks multiple memory chips, has begun to be applied, replacing the conventional two-dimensional (2D) stacking method. In line with the trend of demanding high integration and high-capacity memory, there may be a need for a structure that improves integration density by increasing capacity using a 3D memory chip layout while simultaneously reducing the semiconductor chip size. As such a three-dimensional stacking technology, the Through Silicon Via (TSV) method is being used, which is a packaging technology that connects the top and bottom of a semiconductor chip with a silicon through-electrode by drilling a tiny hole in the semiconductor chip. In a three-dimensional integrated circuit, a test of a TSV (Through-Silicon-Via) can be performed to identify resistive open or short-circuit defects in the TSV by measuring the voltage passing through the TSV, calculating the resistance value of the TSV, and converting it into data. Conventional TSV test circuits including flip-flops and comparators can detect open and/or short-circuit defects of TSVs, but the types of defects that can be detected are limited, testing takes a relatively long time, and the accuracy of defect detection is low. Therefore, there is a need for a TSV test circuit that can reduce the time to test TSV failures without additional hardware overhead and can quickly and accurately test various types of TSV failures. FIG. 1 is a block diagram schematically illustrating a semiconductor device (100) including TSV(s) (15) and a TSV test device (10) according to an exemplary embodiment of the present disclosure. FIG. 2 is a block diagram showing the structure of a TSV test device (200) according to an exemplary embodiment of the present disclosure. FIG. 3a is a circuit diagram showing the structure of a VDD control circuit (300a) according to an exemplary embodiment of the present disclosure. FIG. 3b is a circuit diagram showing the structure of a GND control circuit (300b) according to an exemplary embodiment of the present disclosure. FIGS. 4a to 4c are circuit diagrams showing the structure of a TSV test circuit (400) including a first TSV (40) and a second TSV (42). Figure 5 shows a graph (500) of TSV voltage (V_TSV) and PIN voltage (V_PIN) according to the internal resistance of the TSV. FIG. 6 exemplarily shows a timing diagram (600) of the results of measuring the TSV voltage (V_TSV) and PIN voltage (V_PIN) of FIG. 5 according to the clock signal (CLK). FIG. 7 is a block diagram showing a test system (1000) including a semiconductor device (1200) according to an exemplary embodiment of the present disclosure. FIG. 8 is a block diagram showing an example in which the semiconductor device (1200) of FIG. 7 is implemented as HBM (high bandwidth memory). FIG. 9 is a flowchart showing an example of the operation method of the semiconductor device (100) of FIG. 1. FIG. 10 is a block diagram illustrating an exemplary computing system (1300) according to an exemplary embodiment of the present disclosure. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. FIG. 1 is a block diagram schematically illustrating a semiconductor device (100) including TSV(s) (15) and a TSV test device (10) according to an exemplary embodiment of the present disclosure. Referring to FIG. 1, a semiconductor device (100) may include TSV(s) (15) and a TSV test device (10). The TSV(s) (15) and the TSV test device (10) may be connected, and the TSV(s) (15) may include N TSVs, namely, the first TSV to the nth TSV (TSV1 to TSVn). For example, the first TSV to the nth TSV (TSV1 to TSVn) may be formed by physical wiring penetrating a DRAM die (not shown) and may be stacked by microbumps (μbumps). The first TSV to the nth TSV (TSV1 to TSVn) may be used to stack a plurality of DRAM dies. For example, the first to fourth TSVs (TSV1 to TSV4) can be applied to a 4-Stack High Bandwidth Memory (HBM). As an example of implementation, a 4-Stack HBM including the first to fourth TSVs (TSV1 to TSV4) may be defined as a semiconductor device. The TSV test device (10) is a device for testing failures of a TSV (through-silicon-via) and may include a VDD control circuit, a GND control circuit (12_1, 12_2), a TSV test circuit (14), and a defect detector circuit (16). The VDD control circuit (12_1) can be connected to the TSV test circuit (14) and can control the connectio