KR-102963953-B1 - Three-dimensional(3D) storage device using wafer-to-wafer bonding

KR102963953B1KR 102963953 B1KR102963953 B1KR 102963953B1KR-102963953-B1

Abstract

A three-dimensional storage device utilizing wafer-to-wafer bonding is disclosed. In the storage device, a first chip having a peripheral circuit region formed therein including a first control logic circuit for controlling the operating modes of a non-volatile memory device and a second chip having a three-dimensional array of non-volatile memory cells formed therein are wafer-bonded, and the memory controller includes a third chip having a control circuit region formed therein. A second control logic circuit related to the operating conditions of the non-volatile memory device is disposed in the control circuit region of the third chip, and the second control logic circuit includes a serializer/deserializer (SERDES) interface that shares the random access memory of the memory controller and transmits and receives data with the non-volatile memory device.

Inventors

오은주
석준영
송영걸
장병철
임준성

Assignees

삼성전자주식회사

Dates

Publication Date: 20260511
Application Date: 20210825

Claims (10)

In a storage device, A non-volatile memory device comprising non-volatile memory cells; and It includes a memory controller that controls the above-mentioned non-volatile memory device, and The above-mentioned non-volatile memory device is, A first chip having a peripheral circuit region formed therein, the peripheral circuit region including a first control logic circuit for controlling the operation modes of the above-mentioned non-volatile memory device, wherein the peripheral circuit region is disposed on a first surface of a first substrate of the first chip; and A second chip having a three-dimensional array of the above-mentioned non-volatile memory cells formed thereon, wherein the three-dimensional array is disposed on a first surface of a second substrate of the second chip, and the second chip is vertically stacked on the first chip so that the first surface of the first substrate and the first surface of the second substrate are bonded. The above memory controller is, A third chip is provided having a control circuit region formed therein, the control circuit region comprising circuits for setting and changing operating conditions for the non-volatile memory device, wherein the control circuit region is disposed on a first surface of a third substrate of the third chip. A second control logic circuit related to the operating conditions of the above-mentioned non-volatile memory device is disposed on the first surface of the third substrate of the above-mentioned third chip, and In the control circuit region of the third chip, A processor configured to control the operation of the above memory controller; and It includes a random access memory configured as an operating memory of the above-mentioned memory controller, and The above second control logic circuit is a storage device that shares the above random access memory.
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In paragraph 1, In the control circuit region of the third chip, It further includes a memory management unit that changes operating conditions for the non-volatile memory device based on the degradation state of the non-volatile memory device, and The above second control logic circuit is a storage device positioned adjacent to and connected to the memory management unit.
In paragraph 1, The above second control logic circuit is a storage device that is a scheduler controlling at least one of the voltage level, application timing, application time, and number of applications of the corresponding control signals according to the operation mode of the non-volatile memory device.
In a storage device, A plurality of non-volatile memory devices including non-volatile memory cells; and It includes a memory controller that controls the plurality of non-volatile memory devices mentioned above, and Each of the above plurality of non-volatile memory devices is, A first chip having a peripheral circuit region formed therein, the peripheral circuit region including a first control logic circuit for controlling the operating modes of the non-volatile memory device, wherein the peripheral circuit region is disposed on a first surface of a first substrate of the first chip; and A second chip having a three-dimensional array of the above-mentioned non-volatile memory cells formed thereon, wherein the three-dimensional array is disposed on a first surface of a second substrate of the second chip, and the second chip is vertically stacked on the first chip so that the first surface of the first substrate and the first surface of the second substrate are bonded. The above memory controller is, A third chip comprising a control circuit region formed therein, the control circuit region comprising circuits for setting and changing operating conditions for each of the plurality of non-volatile memory devices, wherein the control circuit region is disposed on a first surface of a third substrate of the third chip, and the control circuit region comprises a serializer/deserializer (SERDES) interface for transmitting and receiving data with the plurality of non-volatile memory devices. A second control logic circuit related to the operating conditions of the above-mentioned non-volatile memory device is a storage device disposed on the first surface of the third substrate of the above-mentioned third chip.
In paragraph 5, The above second control logic circuit is a storage device positioned adjacent to and connected to the above SERDES interface.
In paragraph 6, The above SERDES interface is A parallel-to-serial circuit that serializes and transmits a parallel data stream from the memory controller to each of the plurality of non-volatile memory devices; and A storage device comprising a serial-to-parallel circuit that receives a serial data stream transmitted from each of the plurality of non-volatile memory devices and parallelizes the received serial data stream.
In a storage device, A non-volatile memory device comprising non-volatile memory cells; and It includes a memory controller that controls the above-mentioned non-volatile memory device, and The above-mentioned non-volatile memory device is, A first chip having a peripheral circuit region formed therein, comprising a control logic circuit for controlling the operation modes of the non-volatile memory device; the first chip having a control circuit region formed therein, comprising a memory management unit for setting and changing operation conditions for the non-volatile memory device constituting the memory controller; and the peripheral circuit region and the control circuit region are disposed on a first surface of a first substrate of the first chip; and A second chip having a three-dimensional array of the above-mentioned non-volatile memory cells formed thereon, wherein the three-dimensional array is disposed on a first surface of a second substrate of the second chip, and the second chip is vertically stacked on the first chip so that the first surface of the first substrate and the first surface of the second substrate are bonded. The above control logic circuit is a storage device positioned adjacent to and connected to the memory management unit.
In paragraph 8, In the peripheral circuit region of the first chip, A row decoder connected to the word lines of the above non-volatile memory cells; and It further includes a page buffer connected to the bitlines of the above-mentioned non-volatile memory cells, and The row decoder and the page buffer are disposed in the edge region of the first substrate of the first chip, and A storage device in which the control circuit region is disposed inside the edge region of the first substrate of the first chip.
In Paragraph 9, The control circuit region of the first chip is, It further includes an ECC (Error Correction Code) processing unit that detects and corrects errors in data transmitted between the above-mentioned non-volatile memory device and the above-mentioned memory controller, and A storage device in which the page buffer is positioned adjacent to and connected to the ECC processing unit on the first substrate of the first chip.

Description

Three-dimensional (3D) storage device using wafer-to-wafer bonding The present invention relates to a semiconductor device, and more specifically, to a three-dimensional storage device utilizing wafer-to-wafer bonding. Systems using semiconductor chips widely use Dynamic Random Access Memory (DRAM) as operational memory or main memory to store data or instructions used by a host within the system and/or to perform computational operations, and use storage devices as storage media. Storage devices include non-volatile memory. As the capacity of storage devices increases, the number of memory cells and word lines stacked on the substrate of non-volatile memory increases, and the number of data bits stored in the memory cells also increases. To improve the storage capacity and integration density of memory, non-volatile memory devices that stack memory cells in a three-dimensional structure, such as 3D NAND flash memory, are being researched. Research is also continuing on storage devices capable of stable and fast real-time processing of large amounts of data using 3D NAND flash memory. FIG. 1 is a block diagram showing a storage device according to embodiments of the present invention. FIG. 2 is an exemplary block diagram showing the NVM device of FIG. 1. Figure 3 is a diagram illustrating the structure of the NVM device of Figure 2. Figure 4 shows an equivalent circuit diagram of the memory block of Figure 2. Figure 5 illustrates exemplary graphs showing the movement of the threshold voltage dispersion of the memory cells of Figure 4. FIG. 6 is a drawing showing a first example in which the storage device of FIG. 1 is implemented by 3D wafer-to-wafer bonding. FIG. 7 is a drawing showing a second example in which the storage device of FIG. 1 is implemented with 3D wafer-to-wafer bonding. FIG. 8 is a drawing showing a third example in which the storage device of FIG. 1 is implemented with 3D wafer-to-wafer bonding. FIG. 9 is a block diagram conceptually illustrating a system according to embodiments of the present invention. FIG. 10 is a diagram showing an example in which the storage device of FIG. 9 is implemented with 3D wafer-to-wafer bonding. FIG. 11 is a drawing illustrating a system to which a storage device according to embodiments of the present invention is applied. FIG. 12 is a drawing showing a data center to which a storage device according to one embodiment of the invention is applied. FIG. 1 is a block diagram showing a storage device according to embodiments of the present invention. Referring to FIG. 1, the storage device (100) may include a memory device (110) and a memory controller (120). In this embodiment, a number of conceptual hardware configurations included in the storage device (100) are illustrated, but are not limited thereto and other configurations are also possible. The memory controller (120) may control the memory device (110) to write data to the memory device (110) in response to a write request from a host, or control the memory device (110) to read data stored in the memory device (110) in response to a read request from a host. In some embodiments, the storage device (100) may be an internal memory embedded in an electronic device. For example, the storage device (100) may be an embedded Universal Flash Storage (UFS) memory device, an embedded Multi-Media Card (eMMC), or a Solid State Drive (SSD). In some embodiments, the storage device (100) may be an external memory that is detachable from the electronic device. For example, the storage device (100) may include at least one of a UFS memory card, Compact Flash (CF), Secure Digital (SD), Micro Secure Digital (Micro-SD), Mini Secure Digital (Mini-SD), Extreme Digital (xD), and Memory Stick. The memory device (110) can perform write operations or read operations, etc., under the control of the memory controller (120). The memory device (110) receives commands and addresses from the memory controller (120) through input/output lines and transmits and receives data for write operations or read operations with the memory controller (120). Additionally, the memory device (110) can receive control signals through control lines. The memory device (110) may include a control logic circuit (114) and a memory cell array (116). The control logic circuit (114) can control various operations of the memory device (110) overall. The control logic circuit (114) receives a command/address from the memory controller (120) and can generate control signals to control the components of the memory device (110) according to the received command/address. For example, the control logic circuit (114) can use the control signals to store data in the memory cell array (116) or to read the stored data from the memory cell array (116) and output it to the memory controller (120). The memory cell array (116) may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present invention is n