KR-102963954-B1 - SEMICONDUCTOR PACKAGE

Abstract

A semiconductor package according to the technical concept of the present invention comprises a first substrate having a first bump pad and a filling compensation layer disposed around the first bump pad, a second substrate having a second bump pad facing the first substrate, a bump structure in contact with the first bump pad and the second bump pad, and a non-conductive film disposed between the first substrate and the second substrate and surrounding the bump structure, wherein the non-conductive film covers the upper surface and edge of the filling compensation layer.

Inventors

• 김태형
• 송현준
• 안정석

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260511

Application Date

20210726

Claims (10)

1. A first substrate having a first bump pad and a filling compensation layer disposed around the first bump pad; A second substrate facing the first substrate and having a second bump pad; A bump structure in contact with the first bump pad and the second bump pad; and A non-conductive film surrounding the bump structure and disposed between the first substrate and the second substrate; comprising The above non-conductive film covers the upper surface and edges of the above-mentioned filling compensation layer, and The level of the upper surface of the filling compensation layer is higher than the level of the upper surface of the first bump pad. Semiconductor package.
2. delete
3. In paragraph 1, A semiconductor package characterized in that the lower part of the above bump structure contacts the side wall of the above-described filling compensation layer.
4. In paragraph 1, A semiconductor package characterized in that the edge of the filling compensation layer and the edge of the second substrate are located on the same plane in the vertical direction.
5. In paragraph 4, A semiconductor package characterized in that the horizontal width of the fillet area of the non-conductive film protruding outward from the edge of the filling compensation layer and the edge of the second substrate is 100 μm or less.
6. In paragraph 1, The above-mentioned filling compensation layer has a first thickness, and A semiconductor package characterized in that the above-mentioned non-conductive film has a second thickness greater than the above-mentioned first thickness.
7. In paragraph 1, The side wall of the first bump pad is in contact with the filling compensation layer, and A semiconductor package characterized in that the sidewall of the second bump pad is in contact with the non-conductive film.
8. In Paragraph 7, The above non-conductive film comprises an adhesive resin and a flux, and A semiconductor package characterized in that the above-mentioned filling compensation layer is composed of a silicon-based insulating material or a polymer-based insulating material.
9. In paragraph 1, A first penetrating electrode penetrating the first substrate; and It further includes a second penetrating electrode penetrating the second substrate; and The surface on which the first bump pad is formed is an inactive surface of the first substrate, and A semiconductor package characterized in that the surface on which the second bump pad is formed is the active surface of the second substrate.
10. In Paragraph 9, It further includes one or more substrates stacked on the second substrate, and A semiconductor package characterized by having the filling compensation layer and the non-conductive film disposed between the second substrate and the substrates and between the substrates, respectively.

Description

Semiconductor Package The technical field of the present invention relates to semiconductor packages, and more specifically, to semiconductor packages comprising a non-conductive film. Recently, the demand for portable devices in the electronics market has been rapidly increasing, leading to a continuous demand for the miniaturization and lightweighting of electronic components mounted on these products, such as semiconductor chips. To achieve this miniaturization and lightweighting of electronic components, not only is technology required to reduce the individual size of the mounted components, but also semiconductor packaging technology is needed to integrate multiple semiconductor chips constituting the components into a single package. FIG. 1a is a cross-sectional view showing the main components of a semiconductor package according to one embodiment of the technical concept of the present invention. Figure 1b is an enlarged cross-sectional view showing the BB portion of Figure 1a in enlargement. FIG. 2a is a cross-sectional view showing the main components of a semiconductor package according to another embodiment of the technical concept of the present invention. Figure 2b is an enlarged cross-sectional view showing the BB portion of Figure 2a in enlargement. FIGS. 3 to 5 are cross-sectional views showing the main components of a semiconductor package according to another embodiment of the technical concept of the present invention. FIG. 6 is a flowchart illustrating a method for manufacturing a semiconductor package according to one embodiment of the technical concept of the present invention. FIGS. 7a to 7f are cross-sectional views illustrating a method for manufacturing a semiconductor package according to one embodiment of the technical concept of the present invention in the order of process. FIG. 8 is a schematic diagram showing the configuration of a semiconductor package according to embodiments of the technical concept of the present invention. Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings. FIG. 1a is a cross-sectional view showing the main components of a semiconductor package according to one embodiment of the technical concept of the present invention, and FIG. 1b is an enlarged cross-sectional view showing the BB portion of FIG. 1a enlarged. Referring to FIG. 1a and FIG. 1b together, a semiconductor package (10) is shown comprising a first semiconductor chip (100), a second semiconductor chip (200), a non-conductive film (NCF) bonding the first and second semiconductor chips (100, 200), and a filling compensation layer (FCF) located below the non-conductive film (NCF). Each of the first and second semiconductor chips (100, 200) included in the semiconductor package (10) of the present embodiment may be a memory chip or a logic chip. For example, the first and second semiconductor chips (100, 200) may both be memory chips of the same type, or one of the first and second semiconductor chips (100, 200) may be a memory chip and the other may be a logic chip. The memory chip may be a volatile memory chip, such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), for example, or a non-volatile memory chip, such as PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory). Additionally, the logic chip may be, for example, a microprocessor, an analog device, or a digital signal processor. The first semiconductor chip (100) may include a first substrate (101), a first semiconductor device layer (110), a first wiring layer (120), a first connection pad (130), a first connection terminal (140), a first through electrode (150), and a first bump pad (160). The first substrate (101) is a semiconductor substrate and may have an upper surface (101T) and a lower surface (101B) facing each other. Here, the upper surface (101T) may be referred to as an inactive surface, and the lower surface (101B) may be referred to as an active surface. The first substrate (101) may include a first semiconductor device layer (110) formed on the lower surface (101B) side and a first penetrating electrode (150) penetrating the first substrate (101). The first substrate (101) may be a silicon (Si) wafer including, for example, crystalline silicon, polycrystalline silicon, or amorphous silicon. Alternatively, the first substrate (101) may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). Meanwhile, the first substrate (101) may have a silicon-on-insulator (SOI) structure. For example, the first substrate (101) may include a buried oxide layer. In some embodiments, the first substrate (101) may include a conductive region, for example, an impurity-doped