KR-102963955-B1 - SEMICONDUCTOR PACKAGE COMPRISING HEAT SPREADER

KR102963955B1KR 102963955 B1KR102963955 B1KR 102963955B1KR-102963955-B1

Abstract

The technical concept of the present invention provides a semiconductor package comprising: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip; and a plurality of third semiconductor chips sequentially stacked on the second semiconductor chip, wherein the horizontal width of each of the first semiconductor chip and the second semiconductor chip is greater than the horizontal width of each of the plurality of third semiconductor chips, and the first semiconductor chip and the second semiconductor chip are connected to each other through direct contact of bonding pads.

Inventors

조성은
김영득
김재춘
김태환
오경석

Assignees

삼성전자주식회사

Dates

Publication Date: 20260511
Application Date: 20210827

Claims (10)

First semiconductor chip; A second semiconductor chip stacked on the first semiconductor chip; and A plurality of third semiconductor chips sequentially stacked on the second semiconductor chip; comprising The horizontal width of each of the first semiconductor chip and the second semiconductor chip is greater than the horizontal width of each of the plurality of third semiconductor chips, and The first semiconductor chip and the second semiconductor chip are connected to each other through direct contact of bonding pads, A semiconductor package characterized in that the sides of the first semiconductor chip and the second semiconductor chip are located substantially in the same plane.
In Article 1, A semiconductor package characterized in that the thickness of each of the first semiconductor chip and the second semiconductor chip is thicker than the thickness of each of the plurality of third semiconductor chips.
In Article 1, A semiconductor package characterized in that the ratio of the thickness of each of the first semiconductor chip and the second semiconductor chip to the thickness of the third semiconductor chips is 135% to 195%.
In Article 1, A semiconductor package characterized in that the ratio of the horizontal width of each of the first semiconductor chip and each of the second semiconductor chip to the horizontal width of each of the third semiconductor chips is 110% to 140%.
Interposer; A first semiconductor chip stacked on the above interposer; A dummy chip stacked on the first semiconductor chip; A second semiconductor chip stacked on the above dummy chip; A plurality of third semiconductor chips sequentially stacked on the second semiconductor chip; A heat dissipation structure stacked on the plurality of third semiconductor chips; and A molding layer surrounding the plurality of third semiconductor chips and the heat dissipation structure; comprising The first to plurality of third semiconductor chips and the dummy chip each have a penetrating electrode penetrating each of the semiconductor chips, The horizontal width of each of the first semiconductor chip, the dummy chip, and the second semiconductor chip is greater than the horizontal width of each of the plurality of third semiconductor chips, and The sides of the first semiconductor chip, the dummy chip, and the second semiconductor chip are located substantially in the same plane, characterized by... The first semiconductor chip and the dummy chip are connected to each other through direct contact of bonding pads, and A semiconductor package characterized in that the dummy chip and the second semiconductor chip are connected to each other through direct contact of bonding pads.
In Article 5, A semiconductor package characterized in that the thickness of each of the first semiconductor chip, the dummy chip, and the second semiconductor chip is thicker than the thickness of each of the plurality of third semiconductor chips.
In Article 5, A semiconductor package characterized in that the ratio of the horizontal width of each of the first semiconductor chip, the dummy chip, and the second semiconductor chip to the horizontal width of each of the third semiconductor chips is 115% to 130%.
Interposer; A first semiconductor chip stacked on the above interposer; A second semiconductor chip stacked on the first semiconductor chip; A plurality of third semiconductor chips sequentially stacked on the second semiconductor chip; A fourth semiconductor chip disposed between the second semiconductor chip and the plurality of third semiconductor chips; A heat dissipation structure stacked on the plurality of third semiconductor chips; and A molding layer surrounding the plurality of third semiconductor chips and the heat dissipation structure; comprising The first to fourth semiconductor chips have a through electrode penetrating each of the semiconductor chips, The horizontal width of each of the first semiconductor chip, the second semiconductor chip, and the fourth semiconductor chip is greater than the horizontal width of each of the plurality of third semiconductor chips, and The sides of the first semiconductor chip, the second semiconductor chip, and the fourth semiconductor chip are each located substantially in the same plane, and The first semiconductor chip and the second semiconductor chip are connected to each other through direct contact of bonding pads, and A semiconductor package characterized in that the second semiconductor chip and the fourth semiconductor chip are connected to each other through direct contact of bonding pads.
In Article 8, A semiconductor package characterized by including a dummy chip between the second semiconductor chip and the fourth semiconductor chip.
In Article 8, A semiconductor package characterized in that the thickness of each of the first semiconductor chip, the second semiconductor chip, and the fourth semiconductor chip is thicker than the thickness of each of the plurality of third semiconductor chips.

Description

Semiconductor package comprising a heat spreader The technical concept of the present invention relates to a semiconductor package, and more specifically, to a semiconductor package including a heat dissipation device. As the storage capacity of semiconductor chips increases, there is a growing demand for semiconductor packages containing these chips to become thinner and lighter. Furthermore, there is a trend toward research aimed at incorporating semiconductor chips with various functions within the package and driving them at high speeds. In line with this trend, the need for miniaturization and multifunctionality of semiconductor chips used in electronic components is increasing. Additionally, in the packaging field, active research is being conducted on methods to dissipate heat from within the semiconductor package while miniaturizing the size based on small semiconductor chips. FIGS. 1a to 1c are plan and cross-sectional views of a semiconductor package according to one embodiment of the present invention. FIG. 2 is a planar layout showing the planar arrangement of some components of a semiconductor package according to one embodiment of the present invention. FIGS. 3a to 3e are drawings showing various variations of a semiconductor package according to an embodiment of the present invention. FIG. 4 is a cross-sectional view of a semiconductor package according to one embodiment of the present invention. Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. FIG. 1a is a plan view of a semiconductor package (10) according to one embodiment of the present invention, and FIG. 1b and FIG. 1c are cross-sectional views showing the I-I' portion of the semiconductor package (10) of FIG. 1a. Referring to FIGS. 1a to 1c, the semiconductor package (10) of the present embodiment may include an interposer (100), a first semiconductor chip (210) disposed on the interposer (100), a second semiconductor chip (220) disposed on the first semiconductor chip (210), a plurality of third semiconductor chips (300) disposed on the second semiconductor chip (220), and a heat dissipation structure (400) disposed on the plurality of third semiconductor chips (300). In FIGS. 1b and 1c, a semiconductor package (10) is illustrated as comprising one first semiconductor chip (210), one second semiconductor chip (220), and five third semiconductor chips (300), but is not limited thereto. For example, the semiconductor package (10) may comprise a plurality of first semiconductor chips (210) and/or a plurality of second semiconductor chips (220). In some embodiments, a semiconductor package (10) may comprise four or fewer or six or more third semiconductor chips (300). For example, the third semiconductor chips (300) may comprise 10, 14, or 18 semiconductor chips (200). A plurality of third semiconductor chips (300) may be arranged sequentially along a vertical direction on the second semiconductor chip (220). The semiconductor package (10) of the present invention can improve the heat dissipation performance of the semiconductor package (10) by including semiconductor chips (200) with a wide horizontal width and thickness below a plurality of third semiconductor chips (300). In particular, while a heat dissipation structure (400) is generally attached to the upper surface of a plurality of semiconductor chips (300), a heat dissipation structure (400) is not attached to the lower surface of the semiconductor package (10), so it may not be easy for heat generated on the lower surface of the semiconductor package (10) to escape. The semiconductor package (10) of the present invention may include a heat spreader that performs a heat dissipation function on the lower surface of the semiconductor package (10). Accordingly, heat generated on the lower surface of the semiconductor package (10) can be easily released to the outside of the semiconductor package (10). In addition, by including semiconductor chips (200) as the heat spreader, the thickness (Z direction) of the semiconductor package (10) may not be significantly increased. In some embodiments, the interposer (100) may be an RDL interposer (redistribution layer interposer) (100). The interposer (100) may include an interposer redistribution layer (110). The interposer redistribution layer (110) may include at least one redistribution insulating layer and a plurality of redistribution patterns. The plurality of redistribution patterns may include a plurality of redistribution line patterns and a plurality of redistribution vias. For example, the interposer redistribution layer (110) may include a plurality of stacked redistribution insulating layers. The redistribution insulating layers may be formed of an insulating material, such as a PID (Photo-Imageable Dielectric