KR-102963956-B1 - EQUALIZER, OPERATING METHOD OF EQUALIZER AND SYSTEM INCLUDING EQUALIZER

KR102963956B1KR 102963956 B1KR102963956 B1KR 102963956B1KR-102963956-B1

Abstract

An equalizer according to one aspect of the technical concept of the present disclosure comprises an input amplifier that amplifies and outputs an input signal, a first sampling circuit that generates and outputs first-1 to first-N feedback signals (N is a natural number greater than or equal to 2), a first equalization circuit including a first operation circuit and a second operation circuit, a second sampling circuit that generates and outputs second-1 to second-M feedback signals (M is a natural number greater than or equal to 2), a second equalization circuit including a third operation circuit and a fourth operation circuit, wherein the first operation circuit outputs a weighted sum of the received feedback signals among the first-2 to first-N feedback signals and the second-2 to second-M feedback signals, the second operation circuit outputs a weighted sum of the output signal of the input amplifier, the output signal of the first operation circuit, and the second-1 feedback signal to the first sampling circuit, and the third operation circuit outputs a weighted sum of the received feedback signals among the first-2 to first-N feedback signals and the second-2 to second-M feedback signals. The fourth operation circuit weightedly sums the output signal of the input amplifier, the output signal of the third operation circuit, and the first-1 feedback signal and outputs the result to the second sampling circuit.

Inventors

고경준
김한석
박재현
배준한
송경석
유종재

Assignees

삼성전자주식회사

Dates

Publication Date: 20260512
Application Date: 20211007
Priority Date: 20210611

Claims (10)

Input amplifier that amplifies and outputs an input signal; A first equalization circuit comprising a first sampling circuit, a first operation circuit, and a second operation circuit that generate and output first-1 to first-N feedback signals (N is a finite natural number greater than or equal to 2); and It includes a second equalization circuit comprising a second sampling circuit that generates and outputs 2-1 to 2-M feedback signals (M is a finite natural number greater than or equal to 2), a third operation circuit, and a fourth operation circuit, and The first operation circuit above outputs a weighted sum of the received feedback signals among the first-2 to first-N feedback signals and the second-2 to second-M feedback signals, and The second operation circuit above weightedly sums the output signal of the input amplifier, the output signal of the first operation circuit, and the second-1 feedback signal and outputs the result to the first sampling circuit, and The above third operation circuit outputs a weighted sum of the received feedback signals among the above first-2 to first-N feedback signals and the above second-2 to second-M feedback signals, and The fourth operation circuit weightedly sums the output signal of the input amplifier, the output signal of the third operation circuit, and the first-1 feedback signal and outputs the result to the second sampling circuit. Lighting equipment.
In paragraph 1, The first operation circuit receives the first-a feedback signals (where a is all even numbers greater than or equal to 2 and less than or equal to N) and the second-b feedback signals (where b is all odd numbers greater than or equal to 2 and less than or equal to M). Lighting equipment.
In paragraph 2, The above first operation circuit is A plurality of first multipliers that multiply a coefficient by each of the first-a feedback signals and the second-b feedback signals; and A first summer that sums the output values of the plurality of first multipliers. Lighting equipment.
In paragraph 1, The above second operation circuit is A plurality of second multipliers that multiply coefficients by each of the output signal of the first operation circuit and the second-1 feedback signal; and A second summer that sums the output signal of the input amplifier and the output values of the plurality of second multipliers Lighting equipment.
In paragraph 1, The third operation circuit outputs a weighted sum of the first-c feedback signals (where c is all odd numbers greater than or equal to 2 and less than or equal to N) and the second-d feedback signals (where d is all even numbers greater than or equal to 2 and less than or equal to M). Lighting equipment.
In paragraph 5, The above third operation circuit is A plurality of third multipliers that multiply coefficients by each of the first-c feedback signals and the second-d feedback signals; and A third summer that sums the output values of the plurality of third multipliers. Lighting equipment.
In paragraph 1, The above-mentioned fourth operation circuit is A plurality of fourth multipliers that multiply coefficients by each of the output signal of the third operation circuit and the first-1 feedback signal; and A fourth summer that sums the output signal of the input amplifier and the output values of the plurality of fourth multipliers Lighting equipment.
A step of amplifying the input signal through an input amplifier; A step of generating 1-1 to 1-N feedback signals (N is a finite natural number greater than or equal to 2) through a first sampling circuit; A step of generating 2-1 to 2-M feedback signals (M is a finite natural number greater than or equal to 2) through a second sampling circuit; A step of weighted summing the received feedback signals among the first-2 to first-N feedback signals and the second-2 to second-M feedback signals through a first operation circuit; A step of weighted summing the received feedback signals among the first-2 to first-N feedback signals and the second-2 to second-M feedback signals through a third operation circuit; A step of weighted summing the output signal of the input amplifier, the output signal of the first operation circuit, and the second-1 feedback signal through the second operation circuit and outputting the result to the first sampling circuit; and The method includes the step of weighting and summing the output signal of the input amplifier, the output signal of the third operation circuit, and the first-1 feedback signal through the fourth operation circuit and outputting the result to the second sampling circuit. Method of operation of the lighting device.
In paragraph 8, The second operation circuit is connected to the output node of the input amplifier, the output node of the first operation circuit, the output node of the second-1 feedback signal of the second sampling circuit, and the input node of the first sampling circuit. Method of operation of the lighting device.
In paragraph 8, The above-mentioned fourth operation circuit is connected to the output node of the input amplifier, the output node of the third operation circuit, the output node of the first-1 feedback signal of the first sampling circuit, and the input node of the second sampling circuit. Method of operation of the lighting device.

Description

EQUALIZER, OPERATING METHOD OF EQUALIZER AND SYSTEM INCLUDING EQUALIZER The technical concept of the present disclosure relates to an equalizer, and more specifically, to an equalizer in which each equalizer circuit includes two operation circuits. Communication between devices or chips can be achieved through an interface. During this communication process, signals may be distorted when transmitted between devices or chips. To compensate for such signal distortion, the interface may include an equalizer. An equalizer can generate multiple feedback signals and perform the operation of summing the multiple feedback signals and the input signal through an adder. The adder receives the multiple feedback signals and the input signal, sums them, and outputs the summed result to multiple sensing amplifiers. In this case, since multiple sensing amplifiers, output nodes for multiple feedback signals, and input nodes for the input signal are connected to the adder, a problem may arise where it is difficult to secure sufficient bandwidth for the adder. Therefore, it is necessary to develop an equalizer capable of securing sufficient bandwidth for the adder. FIG. 1 is a drawing showing a lighting device according to one embodiment of the present disclosure. FIG. 2 is a drawing showing the first sampling circuit of an equalizer according to one embodiment of the present disclosure in more detail. FIG. 3 is a drawing showing a second sampling circuit of an equalizer according to one embodiment of the present disclosure in more detail. FIG. 4 is a drawing showing the first operation circuit of an equalizer according to one embodiment of the present disclosure in more detail. FIG. 5 is a drawing showing the second operation circuit of an equalizer according to one embodiment of the present disclosure in more detail. FIG. 6 is a drawing showing the third operation circuit of an equalizer according to one embodiment of the present disclosure in more detail. FIG. 7 is a drawing showing the fourth operation circuit of an equalizer according to one embodiment of the present disclosure in more detail. FIG. 8 is a flowchart illustrating a method of operation of a lighting device according to one embodiment of the present disclosure. FIG. 9 is a drawing showing a system including a lighting device according to one embodiment of the present disclosure. FIG. 10 is a drawing showing a system-on-chip including an equalizer according to one embodiment of the present disclosure. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. FIG. 1 is a drawing showing a lighting device according to one embodiment of the present disclosure. Referring to FIG. 1, an equalizer (10) according to one embodiment of the present disclosure may include an input amplifier (100), a first equalization circuit (200), and a second equalization circuit (300). The input amplifier (100) can amplify and output an input signal (IN). More specifically, the input amplifier (100) can receive an input signal (IN) input from the outside. The input amplifier (100) can amplify the received input signal (IN). The input amplifier (100) can output the amplified input signal (IN_A) to the first equalization circuit (200) and the second equalization circuit (300). The first equalization circuit (200) may include a first sampling circuit (210), a first operation circuit (220), and a second operation circuit (230). The first sampling circuit (210) may include a plurality of sensing amplifiers and a plurality of latches. The first sampling circuit (210) may generate and output first-1 to first-N feedback signals (N is a natural number greater than or equal to 2) through the plurality of sensing amplifiers and a plurality of latches. The first sampling circuit (210) can output the first-1 feedback signal (F1-1) to the fourth operation circuit (330) described later. The first sampling circuit (210) can output the first-a feedback signals (where a is all even numbers greater than or equal to 2 and less than or equal to N) among the first-2 to first-N feedback signals to the first operation circuit (220), and output the first-c feedback signals (where c is all odd numbers greater than or equal to 2 and less than or equal to N) to the third operation circuit (320). For example, when N=5, the first sampling circuit (210) can output the first-2 feedback signal (F1-2) and the first-4 feedback signal (F1-4) to the first operation circuit (220), and output the first-3 feedback signal (F1-3) and the first-5 feedback signal (F1-5) to the third operation circuit (320). The first operation circuit (220) can receive some of the first-2 to first-N feedback signals and the second-2 to second-M feedback signals (M is a natural number greater than or equal to 2). More specifically, the first operation circuit (220) can receive first-a feedback signals from the first sampling circuit (210). And the first operation circuit (220) can r