KR-102963957-B1 - SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME

KR102963957B1KR 102963957 B1KR102963957 B1KR 102963957B1KR-102963957-B1

Abstract

The technical concept of the present invention provides a semiconductor package comprising: a package substrate including a first mounting region and a second mounting region; a first semiconductor chip disposed on the first mounting region of the package substrate; a second semiconductor chip disposed on the second mounting region of the package substrate; an interposer substrate disposed on the second mounting region of the package substrate and covering the second semiconductor chip; conductive connectors extending between the interposer substrate and the package substrate and spaced laterally from the second semiconductor chip; and a third semiconductor chip on the interposer substrate; wherein the distance between the upper surface of the first semiconductor chip and the package substrate is greater than the distance between the upper surface of the interposer substrate and the package substrate.

Inventors

최윤석
심종보
강희엽
조성은

Assignees

삼성전자주식회사

Dates

Publication Date: 20260511
Application Date: 20220427

Claims (20)

A package substrate including a first mounting area and a second mounting area; A first semiconductor chip disposed on the first mounting area of the package substrate; A second semiconductor chip disposed on the second mounting area of the package substrate; An interposer substrate disposed on the second mounting region of the package substrate and covering the second semiconductor chip; Conductive connectors extending between the interposer substrate and the package substrate and spaced laterally from the second semiconductor chip; and A third semiconductor chip on the interposer substrate above; Includes, The distance between the upper surface of the first semiconductor chip and the package substrate is greater than the distance between the upper surface of the interposer substrate and the package substrate, and The horizontal width of the first semiconductor chip is greater than the horizontal width of the second semiconductor chip and the horizontal width of the third semiconductor chip, and The distance between the upper surface of the interposer substrate and the package substrate is 200 μm or less, and A semiconductor package in which the distance between the upper surface of the first semiconductor chip and the package substrate is greater than 200㎛ and less than or equal to 1000㎛.
In Article 1, The thickness of the first semiconductor chip is greater than the thickness of the second semiconductor chip and the thickness of the third semiconductor chip, and A semiconductor package characterized in that the upper surface of the first semiconductor chip is exposed to the outside of the semiconductor package.
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In Article 1, A semiconductor package characterized in that the distance between the upper surface of the second semiconductor chip and the package substrate is 100㎛ or less.
In Article 1, A first passive element disposed on the second mounting region of the package substrate; and A second passive element attached to the lower surface of the above interposer substrate; A semiconductor package characterized by further including
In Article 1, A third passive element attached to the lower surface of the above-mentioned package substrate; and An external connection terminal attached to the lower surface of the above-mentioned package substrate; Includes more, A semiconductor package characterized in that the distance between the bottom of the third passive element and the bottom surface of the package substrate is smaller than the distance between the bottom of the external connection terminal and the bottom surface of the package substrate.
In Article 1, The first semiconductor chip above includes a logic chip, and The second semiconductor chip above includes at least one of a power management integrated circuit chip and a radio frequency integrated circuit chip, and A semiconductor package characterized in that the third semiconductor chip includes a memory chip.
In Article 1, A semiconductor package characterized by further including a heat sink in direct contact with the upper surface of the first semiconductor chip.
In Article 1, It further includes a first molding layer surrounding the sidewall of the first semiconductor chip, and A semiconductor package characterized in that the first molding layer does not cover the upper surface of the first semiconductor chip.
In Article 9, A second molding layer disposed on the interposer substrate and covering the third semiconductor chip; further comprising The first molding layer is provided between the interposer substrate and the package substrate and further includes a portion in contact with the second semiconductor chip and the conductive connectors. The first molding layer has a stepped upper surface having a first upper surface and a second upper surface, The first upper surface of the first molding layer is coplanar with the upper surface of the first semiconductor chip, and The second upper surface of the first molding layer is coplanar with the upper surface of the interposer substrate, and The second upper surface of the first molding layer is positioned at a lower level than the first upper surface, and A semiconductor package characterized in that the second molding layer is spaced apart from the first molding layer.
In Article 10, A semiconductor package characterized in that the first molding layer does not cover the upper surface of the interposer substrate.
A package substrate including a first mounting area and a second mounting area; A first semiconductor chip disposed on the first mounting area of the package substrate; First chip connection bumps disposed between the first semiconductor chip and the package substrate; A second semiconductor chip disposed on the second mounting area of the package substrate; Second chip connection bumps disposed between the second semiconductor chip and the package substrate; An interposer substrate disposed on the second mounting region of the package substrate to cover the second semiconductor chip; A first passive element disposed on the second mounting region of the package substrate; A second passive element attached to the lower surface of the interposer substrate and spaced apart from the package substrate; Conductive connectors extending from the interposer substrate to the package substrate and spaced laterally from the second semiconductor chip; A third semiconductor chip on the interposer substrate above; A third passive element attached to the lower surface of the above-mentioned package substrate; and An external connection terminal attached to the lower surface of the above-mentioned package substrate; Includes, The distance between the upper surface of the interposer substrate and the package substrate is 200 μm or less, and The distance between the upper surface of the first semiconductor chip and the package substrate is greater than 200㎛ and less than or equal to 1000㎛, The height of the third passive component measured with respect to the lower surface of the package substrate is smaller than the height of the external connection terminal. Semiconductor package.
In Article 12, The horizontal width of the first semiconductor chip is greater than the horizontal width of the second semiconductor chip and the horizontal width of the third semiconductor chip, and The thickness of the first semiconductor chip is greater than the thickness of the second semiconductor chip and the thickness of the third semiconductor chip, and The first semiconductor chip above includes a logic chip, and The second semiconductor chip above includes at least one of a power management integrated circuit chip and a radio frequency integrated circuit chip, and The above-mentioned third semiconductor chip includes a memory chip, and A semiconductor package characterized by further including a heat sink in contact with the upper surface of the first semiconductor chip.
In Article 12, A first underfill layer disposed between the first semiconductor chip and the package substrate and surrounding the sidewalls of the first chip connection bumps; and A second underfill layer disposed between the second semiconductor chip and the package substrate and surrounding the sidewalls of the second chip connection bumps; A semiconductor package characterized by further including
In Article 12, The apparatus further comprises the first semiconductor chip, the second semiconductor chip, the interposer substrate, and a molding layer in contact with the conductive connectors. A semiconductor package characterized in that the molding layer does not cover the upper surface of the first semiconductor chip and the upper surface of the interposer substrate.
A package substrate including a first mounting area and a second mounting area; A first semiconductor chip disposed on the first mounting area of the package substrate; A second semiconductor chip disposed on the second mounting area of the package substrate; An interposer substrate disposed on the second mounting region of the package substrate and covering the second semiconductor chip; Conductive connectors extending between the interposer substrate and the package substrate and spaced laterally from the second semiconductor chip; A third semiconductor chip on the interposer substrate above; An external connection terminal attached to the lower surface of the above-mentioned package substrate; A system board disposed below the above package substrate and connected to the external connection terminal; and A structure in contact with the upper surface of the first semiconductor chip and comprising at least one of a heat sink and a thermal interface material layer; Includes, The distance between the upper surface of the first semiconductor chip and the package substrate is greater than the distance between the upper surface of the interposer substrate and the package substrate, and The horizontal width of the first semiconductor chip is greater than the horizontal width of the second semiconductor chip and the horizontal width of the third semiconductor chip, and The distance between the upper surface of the interposer substrate and the package substrate is 200 μm or less, and An electronic device in which the distance between the upper surface of the first semiconductor chip and the package substrate is greater than 200 μm and less than or equal to 1000 μm.
In Article 16, A first passive element disposed on the second mounting region of the package substrate; and A second passive element attached to the lower surface of the above interposer substrate; A third passive element attached to the lower surface of the package substrate and spaced apart from the system board; Includes more, An electronic device characterized in that the thickness of the first semiconductor chip is greater than the thickness of the second semiconductor chip and the thickness of the third semiconductor chip.
In Article 16, The difference between the distance between the upper surface of the first semiconductor chip and the package substrate and the distance between the upper surface of the interposer substrate and the package substrate is 200㎛ or more, and An electronic device characterized in that the distance between the upper surface of the second semiconductor chip and the package substrate is 100㎛ or less.
In Article 16, The first semiconductor chip above includes a logic chip, and The second semiconductor chip above includes at least one of a power management integrated circuit chip and a radio frequency integrated circuit chip, and An electronic device characterized in that the above-mentioned third semiconductor chip includes a memory chip.
In Article 16, The apparatus further comprises the first semiconductor chip, the second semiconductor chip, the interposer substrate, and a molding layer in contact with the conductive connectors. An electronic device characterized in that the above molding layer does not cover the upper surface of the above interposer substrate.

Description

Semiconductor package and electronic device including the same The technical concept of the present invention relates to a semiconductor package and an electronic device including the same, and more specifically, to a semiconductor package including a plurality of semiconductor chips and an electronic device including said semiconductor package. Driven by the rapid development of the electronics industry and user demands, electronic devices are becoming increasingly smaller, multifunctional, and high-capacity. Consequently, semiconductor packages containing multiple semiconductor chips are in demand. For example, methods may be used to mount various types of semiconductor chips side-by-side on a single package substrate, or to stack semiconductor chips or packages on a single package substrate. FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. Figure 2 is a plan view showing some components of the semiconductor package of Figure 1. FIG. 3 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. FIG. 4 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. FIG. 5 is a cross-sectional view showing an electronic device according to exemplary embodiments of the present invention. FIGS. 6a to 6e are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments of the present invention. Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. FIG. 1 is a cross-sectional view showing a semiconductor package (100) according to exemplary embodiments of the present invention. FIG. 2 is a plan view showing some components of the semiconductor package (100) of FIG. 1. Referring to FIGS. 1 and 2, a semiconductor package (100) may include a package substrate (110), a first semiconductor chip (120), a second semiconductor chip (130), an interposer substrate (140), a sub-package (150) including a third semiconductor chip (153), and first to third passive elements (181, 183, 185). The package substrate (110) may generally have a flat plate or panel shape. The package substrate (110) may include an upper surface (119) and a lower surface (118) opposite each other, and the upper surface (119) and the lower surface (118) may each be flat. In the following, the horizontal direction (e.g., X direction and/or Y direction) may be defined as a direction parallel to the upper surface (119) of the package substrate (110), the vertical direction (e.g., Z direction) may be defined as a direction perpendicular to the upper surface (119) of the package substrate (110), and the horizontal width may be defined as a length along the horizontal direction (e.g., X direction and/or Y direction). The package substrate (110) may include a first mounting area (R1) and a second mounting area (R2) spaced apart from each other. A first semiconductor chip (120) may be placed on the first mounting area (R1) of the package substrate (110). A second semiconductor chip (130), an interposer substrate (140), and a sub-package (150) may be placed on the second mounting area (R2) of the package substrate (110). The package substrate (110) may be, for example, a printed circuit board (PCB). The package substrate (110) may include a core insulating layer (111), first upper connection pads (112), second upper connection pads (113), third upper connection pads (114), and lower connection pads (115). The core insulating layer (111) may include at least one material selected from phenolic resin, epoxy resin, and polyimide. For example, the core insulating layer (111) may include at least one material selected from polyimide, FR-4 (Flame Retardant 4), tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, BT (Bismaleimide triazine), Thermount, cyanate ester, and liquid crystal polymer. First upper connection pads (112), second upper connection pads (113), and third upper connection pads (114) may be provided on the upper surface of the core insulating layer (111). The first upper connection pads (112) may be provided within the first mounting area (R1) of the package substrate (110), and the second upper connection pads (113) and third upper connection pads (114) may be provided within the second mounting area (R2) of the package substrate (110). Lower connection pads (115) may be provided on the lower surface of the core insulating layer (111). Internal wiring electrically and physically connected to the first upper connection pads (112), second upper connection pads (113), third upper connection pads (114), and lower connection pads (115) may be provided inside the core insulatin