KR-102963969-B1 - PROCESSOR AND ELECTRONIC DEVICE INCLUDING THE SAME

Abstract

The electronic device may include a host processor including a data transmission unit, a driving driver, and a display panel. The data transmission unit includes a phase-locked loop that generates a first clock and a second clock, a clock block that receives the first clock, a plurality of data blocks that receive the second clock, a first buffer connected between the phase-locked loop and the clock block, and a plurality of second buffers each connected between the phase-locked loop and the plurality of data blocks, and each of the first buffer and the plurality of second buffers may be configured to be enabled or disabled according to the interface mode.

Inventors

• 배종만
• 김준달
• 김현수
• 박동원
• 송준용
• 진태영

Assignees

• 삼성디스플레이 주식회사

Dates

Publication Date

20260513

Application Date

20220215

Claims (20)

1. A host processor including a data transmission unit; A driving driver connected to the above host processor in interface mode and receiving data from the above host processor; and It includes a display panel controlled by the above-mentioned driving driver, and The above data transmission unit is, Phase synchronization loop generating a first clock and a second clock; A clock block that receives the first clock and outputs a clock signal to a clock lane; A plurality of data blocks that receive the second clock and output serial data to a plurality of data lanes, respectively; A first buffer connected between the phase-locked loop and the clock block; and It includes a plurality of second buffers each connected between the above phase-locked loop and the plurality of data blocks, and The first buffer is enabled or disabled according to the interface mode so that the clock block receives or does not receive the first clock, and An electronic device configured such that each of the plurality of second buffers is enabled or disabled according to the interface mode, so that each of the plurality of data blocks receives or does not receive the second clock.
2. In Article 1, The above data transmission unit is, A voltage regulator that generates a voltage provided to the clock block and the plurality of data blocks; and A third buffer connected between the above voltage regulator and the above clock block; and It further includes a plurality of fourth buffers each connected between the voltage regulator and the plurality of data blocks, and An electronic device in which each of the third buffer and the plurality of fourth buffers is configured to be enabled or disabled according to the interface mode.
3. In Article 2, An electronic device configured such that when the above interface mode is a first interface mode, the first buffer, the plurality of second buffers, the third buffer, and the plurality of fourth buffers are all activated.
4. In Paragraph 3, An electronic device configured such that when the above interface mode is a second interface mode different from the above first interface mode, the first buffer and the third buffer are disabled, at least one of the plurality of second buffers is enabled and the remaining second buffers are disabled, and at least one of the plurality of fourth buffers is enabled and the remaining fourth buffers are disabled.
5. In Paragraph 4, In the first interface mode, the clock lane and the plurality of data lanes are all used, and An electronic device configured such that only at least one data lane among the clock lane and the plurality of data lanes is used in the second interface mode.
6. In Paragraph 4, The above plurality of data blocks include a first data block, a second data block, a third data block, and a fourth data block, and The plurality of second buffers include a first clock buffer connected between the first data block and the phase lock loop, a second clock buffer connected between the second data block and the phase lock loop, a third clock buffer connected between the third data block and the phase lock loop, and a fourth clock buffer connected between the fourth data block and the phase lock loop. The above plurality of fourth buffers is an electronic device comprising a first voltage buffer connected between the first data block and the voltage regulator, a second voltage buffer connected between the second data block and the voltage regulator, a third voltage buffer connected between the third data block and the voltage regulator, and a fourth voltage buffer connected between the fourth data block and the voltage regulator.
7. In Article 6, An electronic device configured such that, in the second interface mode, the first clock buffer and the first voltage buffer are enabled, and the second clock buffer, the third clock buffer, the fourth clock buffer, the second voltage buffer, the third voltage buffer, and the fourth voltage buffer are disabled.
8. In Article 6, An electronic device configured such that, in the second interface mode, the first clock buffer, the second clock buffer, the first voltage buffer, and the second voltage buffer are enabled, and the third clock buffer, the fourth clock buffer, the third voltage buffer, and the fourth voltage buffer are disabled.
9. In Article 2, An electronic device further comprising a signal generating unit that generates control signals for controlling the operations of each of the first buffer, the plurality of second buffers, the third buffer, and the plurality of fourth buffers according to the above interface mode.
10. In Article 1, An electronic device in which the distance between the input terminal of the first buffer and the output terminal of the phase-locked loop is shorter than the distance between the output terminal of the first buffer and the input terminal of the clock block.
11. In Article 1, An electronic device in which the distance between each of the input terminals of the plurality of second buffers and the output terminal of the phase-locked loop is shorter than the distances between each of the output terminals of the plurality of second buffers and the input terminals of the plurality of data blocks.
12. In Article 1, Each of the above clock block and the plurality of data blocks is, A clock divider that divides the first clock or the second clock by an integer multiple; A digital processing unit that receives a signal from the above clock divider and processes it digitally; A low-power driver that processes data received from the digital processing unit and outputs a signal to the clock lane or the plurality of data lanes when the data transmitting unit operates in low-power mode; A serial converter that converts data received from the digital processing unit into serial data when the data transmission unit operates in high-speed mode; and An electronic device comprising a high-speed driver that processes the serial data received from the serial converter and outputs a signal to the clock lane or the plurality of data lanes when the data transmitting unit operates in high-speed mode.
13. It includes a data transmitter that outputs data through an interface mode, and The above data transmission unit is, Phase synchronization loop generating a first clock and a second clock; A clock block that receives the first clock and outputs a clock signal to a clock lane; A plurality of data blocks that receive the second clock and output serial data to a plurality of data lanes, respectively; A first buffer connected between the phase-locked loop and the clock block; and It includes a plurality of second buffers each connected between the above phase-locked loop and the plurality of data blocks, and The first buffer is configured to be enabled or disabled according to the interface mode so that the clock block receives or does not receive the first clock, and A processor configured such that each of the plurality of second buffers is enabled or disabled according to the interface mode, so that each of the plurality of data blocks receives or does not receive the second clock.
14. In Article 13, The above data transmission unit is, A voltage regulator that generates a voltage provided to the clock block and the plurality of data blocks; and A third buffer connected between the above voltage regulator and the above clock block; and It further includes a plurality of fourth buffers each connected between the voltage regulator and the plurality of data blocks, and A processor configured such that each of the above-mentioned third buffer and the above-mentioned plurality of fourth buffers is enabled or disabled according to the interface mode.
15. In Article 14, A processor configured such that when the above interface mode is the first interface mode, the first buffer, the plurality of second buffers, the third buffer, and the plurality of fourth buffers are all activated.
16. In Article 15, A processor configured such that when the above interface mode is a second interface mode different from the above first interface mode, the first buffer and the third buffer are disabled, at least one of the plurality of second buffers is enabled and the remaining second buffers are disabled, and at least one of the plurality of fourth buffers is enabled and the remaining fourth buffers are disabled.
17. In Article 14, A processor further comprising a signal generation unit that generates control signals for controlling the operations of each of the first buffer, the plurality of second buffers, the third buffer, and the plurality of fourth buffers according to the above interface mode.
18. In Article 13, A processor in which the distance between the input terminal of the first buffer and the output terminal of the phase-locked loop is shorter than the distance between the output terminal of the first buffer and the input terminal of the clock block.
19. In Article 13, A processor in which the distance between each of the input terminals of the plurality of second buffers and the output terminal of the phase-locked loop is shorter than the distances between each of the output terminals of the plurality of second buffers and the input terminals of the plurality of data blocks.
20. In Article 13, Each of the above clock block and the plurality of data blocks is, A clock divider that divides the first clock or the second clock by an integer multiple; A digital processing unit that receives a signal from the above clock divider and processes it digitally; A low-power driver that processes data received from the digital processing unit and outputs a signal to the clock lane or the plurality of data lanes when the data transmitting unit operates in low-power mode; A serial converter that converts data received from the digital processing unit into serial data when the data transmission unit operates in high-speed mode; and A processor comprising a high-speed driver that, when the data transmitter operates in high-speed mode, processes the serial data received from the serial converter and outputs a signal to the clock lane or the plurality of data lanes.

Description

Processor and electronic device including the same The present invention relates to a processor with reduced power consumption and an electronic device including the same. The electronic device may include a host processor, a driving driver, and a display panel. The host processor transmits input image data to the driving driver, and the driving driver may generate a data signal based on the input image data. The host processor and the driving driver may be connected to each other through a predetermined interface. The host processor includes a data transmission unit, and frame data (or commands) may be transmitted from the host processor to the driving driver. FIG. 1 is a block diagram of an electronic device according to one embodiment of the present invention. FIG. 2 is a block diagram of a data transmission unit according to an embodiment of the present invention. FIG. 3 is a block diagram illustrating a data transmitting unit and a data receiving unit connected in a first interface mode according to an embodiment of the present invention. FIG. 4a is a block diagram illustrating a data transmitting unit and a data receiving unit connected in a second interface mode according to an embodiment of the present invention. Figure 4b is a block diagram of the data transmission unit illustrated in Figure 4a. FIG. 5a is a block diagram illustrating a data transmitting unit and a data receiving unit connected in a second interface mode according to an embodiment of the present invention. FIG. 5b is a block diagram of the data transmission unit illustrated in FIG. 5a. FIG. 6 is a block diagram of a clock block according to one embodiment of the present invention. FIG. 7 is a block diagram of a data block according to one embodiment of the present invention. In this specification, where a component (or region, layer, part, etc.) is described as being “on,” “connected,” or “joined” another component, it means that it may be directly placed/connected/joined on the other component, or that a third component may be placed between them. Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. “And/or” includes all one or more combinations that the associated components may define. Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise. Additionally, terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings. Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. The terms "part" and "unit" refer to software components or hardware components that perform specific functions. Hardware components may include, for example, field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). Software components may refer to executable code and/or data used by executable code within an addressable storage medium. Thus, software components may be, for example, object-oriented software components, class components, and task components, and may include processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, or variables. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein. Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an electronic device according to one embodiment of the present invention. Referring to FIG. 1, the electronic device (ED) may include a host processor (HP, or p