KR-102963978-B1 - RANK-LEVEL ECC DECODING METHOD AND APPARATUS FOR CORRECTING ROW AND COLUMN ERRORS

Abstract

A bidirectional error control RL-ECC decoding device according to one embodiment includes: an RS decoding unit that receives a received codeword as input and corrects a vertical error of less than or equal to t symbols of an RS code; a horizontal error decoding unit that receives the received codeword as input and corrects a horizontal error of more than or equal to t+1 symbols; and a decoding output selection unit that selects either the output of the RS decoding unit or the output of the horizontal error decoding unit to output a decoding result. The decoding output selection unit selects the output of the RS decoding unit if decoding is successful according to the decoding result signal of the RS decoding unit, and selects the output of the horizontal error decoding unit if decoding fails according to the decoding result signal to output the decoding result, wherein in the selection between the output of the RS decoding unit and the output of the horizontal error decoding unit, the output of the RS decoding unit is selected first to output the decoding result.

Inventors

• 김상효
• 김정래
• 홍석인
• 김규리
• 하태욱

Assignees

• 성균관대학교산학협력단

Dates

Publication Date

20260511

Application Date

20250115

Claims (18)

1. An RS decoder that receives a received codeword as input and corrects vertical errors of t symbols or less in the RS (Reed-Solomon) code (errors occurring in the column direction in the RS codeword array); A horizontal error decoder that receives the above-mentioned received codeword as input and corrects horizontal errors of t+1 symbols or more (errors occurring in the row direction in the codeword array of the RS code); and A decoding output selection unit that selects either the output of the RS decoding unit and the output of the horizontal direction error decoding unit to output a decoding result; The above decoding output selection unit selects the output of the RS decoding unit if decoding is successful according to the decoding result signal of the RS decoding unit, and selects the output of the horizontal direction error decoding unit if decoding fails according to the decoding result signal to output the decoding result, wherein in the selection between the output of the RS decoding unit and the output of the horizontal direction error decoding unit, the output of the RS decoding unit is selected first to output the decoding result. Bidirectional error control RL-ECC (rank-level ECC) decoder.
2. In Article 1, The above horizontal direction error decoding unit is, A polynomial syndrome calculator that calculates a polynomial syndrome for the above-mentioned received codeword; A syndrome shift calculator for calculating a syndrome of error patterns cyclically shifted for the above-calculated polynomial syndrome; A horizontal direction error detector that detects and derives a horizontal direction error for the syndrome of the above-calculated error pattern; and Error corrector for correcting the detected and derived horizontal direction error; Bidirectional error control RL-ECC decoder.
3. In Article 2, The above-described polynomial syndrome calculator receives a received codeword vector y as input, performs a matrix multiplication of y and the transpose of the parity check matrix (PCM) H , and calculates a syndrome vector s , which is then provided to the above-described syndrome shift calculator and the above-described horizontal error detector. Bidirectional error control RL-ECC decoder.
4. In Article 2, The above syndrome shift calculator calculates the cyclically shifted syndrome by utilizing the syndrome shift property, which allows calculating a polynomial syndrome corresponding to an error pattern that is cyclically shifted from an arbitrary error pattern through a polynomial syndrome for that error pattern. Bidirectional error control RL-ECC decoder.
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9. As a bidirectional error control RL-ECC decoding method performed by a bidirectional error control RL-ECC decoding device, A step of receiving a received codeword as input and correcting a vertical error of t symbols or less of the RS code (an error occurring in the column direction of the RS codeword array); A step of receiving the above-mentioned received codeword as input and correcting a horizontal error of t+1 symbol or more (an error occurring in the row direction in the codeword array of the RS code); and The method includes the step of selecting either the correction result for t symbols or less or the correction result for t+1 symbols or more to output a decoding result; When outputting the above decoding result, depending on the correction result for the vertical direction error, if decoding is successful, the correction result for the vertical direction error is selected as the above decoding result, and if decoding fails, the correction result for the horizontal direction error is selected as the above decoding result; and in the selection between the correction result for the vertical direction error and the correction result for the horizontal direction error, the correction result for the vertical direction error is selected first as the above decoding result. Bidirectional error control RL-ECC (rank-level ECC) decoding method.
10. In Article 9, The step of correcting the above horizontal direction error is, A step of calculating a polynomial syndrome for the above-mentioned received codeword; A step of calculating a syndrome of a cyclically shifted error pattern for the above-calculated polynomial syndrome; A step of detecting and deriving a horizontal error for the syndrome of the above-calculated error pattern; and A step of correcting the detected and derived horizontal direction error; Bidirectional Error Control RL-ECC Decoding Method.
11. In Article 10, When calculating the above polynomial syndrome, the received codeword vector y is taken as input, and the syndrome vector s is calculated by performing a matrix multiplication of y and the transpose of the parity check matrix (PCM) H, H T. Bidirectional Error Control RL-ECC Decoding Method.
12. In Article 10, When calculating the syndrome of the above-mentioned cyclically shifted error pattern, the syndrome of the above-mentioned cyclically shifted error pattern is obtained by utilizing the syndrome shift property, which allows calculating the polynomial syndrome corresponding to the error pattern that is cyclically shifted through the polynomial syndrome for any error pattern. Bidirectional Error Control RL-ECC Decoding Method.
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17. As a computer-readable recording medium in which a computer program is stored, The above computer program includes instructions for causing the processor to perform a bidirectional error control RL-ECC (rank-level ECC) decoding method when executed by a processor, wherein The above bidirectional error-controlled RL-ECC decoding method is, A step of receiving a received codeword as input and correcting a vertical error of t symbols or less of the RS code (an error occurring in the column direction of the RS codeword array); A step of receiving the above-mentioned received codeword as input and correcting a horizontal error of t+1 symbol or more (an error occurring in the row direction in the codeword array of the RS code); and The method includes the step of selecting either the correction result for t symbols or less or the correction result for t+1 symbols or more to output a decoding result; When outputting the above decoding result, depending on the correction result for the vertical direction error, if decoding is successful, the correction result for the vertical direction error is selected as the above decoding result, and if decoding fails, the correction result for the horizontal direction error is selected as the above decoding result; and in the selection between the correction result for the vertical direction error and the correction result for the horizontal direction error, the correction result for the vertical direction error is selected first as the above decoding result. A computer-readable recording medium in which a computer program is stored.
18. As a computer program stored on a computer-readable recording medium, When the above computer program is executed by a processor, Includes instructions for the processor to perform a bidirectional error control RL-ECC (rank-level ECC) decoding method, wherein The above bidirectional error-controlled RL-ECC decoding method is, A step of receiving a received codeword as input and correcting a vertical error of t symbols or less of the RS code (an error occurring in the column direction of the RS codeword array); A step of receiving the above-mentioned received codeword as input and correcting a horizontal error of t+1 symbol or more (an error occurring in the row direction in the codeword array of the RS code); and The method includes the step of selecting either the correction result for t symbols or less or the correction result for t+1 symbols or more to output a decoding result; When outputting the above decoding result, depending on the correction result for the vertical direction error, if decoding is successful, the correction result for the vertical direction error is selected as the above decoding result, and if decoding fails, the correction result for the horizontal direction error is selected as the above decoding result; and in the selection between the correction result for the vertical direction error and the correction result for the horizontal direction error, the correction result for the vertical direction error is selected first as the above decoding result. A computer program stored on a computer-readable recording medium.

Description

Rank-Level ECC Decoding Method and Apparatus for Correcting Row and Column Errors The present invention relates to a rank-level error correction code (ECC) decoding method capable of correcting row and column errors and a rank-level ECC decoding device for performing such decoding method. Error Correction Code (ECC) detects and corrects errors that may occur during data communication by adding redundant data called parity, and this requires encoding and decoding processes. Today, error correction codes are widely used in the communications field to protect messages from errors and enhance system reliability, and semiconductor memory has also applied error correction codes to address errors that may occur during storage and transmission. Memories such as DRAM (Dynamic Random Access Memory) must transmit data accurately within a short period of time. Early memories, which had very low error probabilities and where single-bit errors were the majority, either did not perform error correction or frequently utilized simple SEC (Single Error Correction) codes performed on a per-chip basis. This was done to account for the space and delay overhead required to store parity and perform encoding and decoding. However, as high integration and low-power operation were pursued to improve the performance of memory semiconductors, the overall error probability increased, and the rate of multi-bit upset (MBU) also rose. Consequently, to maintain memory reliability, rank-level ECC (RL-ECC) was applied by using additional DRAM chips. Semiconductor memory with RL-ECC applied protects the data chip from errors by additionally using a parity chip to store the parity of the error correction code, in addition to the data chip that stores data. Figure 1 illustrates the error correction process during data transmission between the processor and the DRAM. Data u is stored in the cells of the DRAM chip in bit units; before being sent to the DRAM, it is encoded by the memory controller into a codeword c with parity r added to the data and transmitted to the DRAM, and the data and parity bits are stored in the data chip and parity chip, respectively. When reading data stored in DRAM, a codeword containing parity is read. During this process, an error e is added during storage and transmission, resulting in the read codeword (received codeword) y = c + e. This read codeword is decoded by the memory controller and transmitted as data to the processor. While this decoding and decoding process can detect and correct errors that may occur during data storage and transmission, thereby increasing the reliability of DRAM, there are issues such as the need for additional storage space to store parity bits and time delays occurring during the decoding and decoding process. For RL-ECC, error correction codes such as BCH (Bose-Chaudhuri-Hocquenghem) code or RS (Reed-Solomon) code, which are more complex than SEC codes but capable of correcting a wider range of errors, have been applied. Among them, the RS code is an error correction code that performs symbol-unit error correction by grouping multiple bits into a single symbol. It has been adopted as an ECC in various applications, such as broadcasting systems and memory, due to its advantages of satisfying the singleton limit and effectively handling burst errors. There are various methods for grouping bits that constitute the symbol of an RS code in a memory system. In particular, Bamboo ECC, which forms a single symbol using multiple bits output from a single pin, utilizes two DRAM chips (x4 chips) with four DQ pins each as parity chips. It possesses the characteristic of being robust against pin-level errors while simultaneously offering chipkill correction capabilities that correct all errors occurring within the chip, thereby enabling effective response to error situations caused by faults in the DRAM chip and pins. Here, chipkill refers to the ability to correct all error patterns limited to a single chip. However, when a single x8 chip is used as a parity chip, the amount of parity remains the same, but chip kill correction capability cannot be guaranteed. In particular, horizontal errors (errors occurring in the row direction of the RS codeword array) where errors occur simultaneously across multiple pins of a single DRAM chip can result in errors that cannot be corrected by memory ECC using the Bamboo ECC RS code. One type of such horizontal error is caused by anomalies in the DQS (DQ strobe) signal, which determines the moment pins read data on the DRAM chip. As DRAM operating clocks continuously increase in response to rising computing demands, the tendency for such errors to occur is increasing. In this document, we will refer to this type of error as a DQS error. Therefore, additional technology is required to correct these horizontally occurring DQS errors. Figure 1 illustrates the error correction process during data transmission between the processor and the DRAM. Figure 2 is an exa