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KR-102964111-B1 - CMOS inverter and method of manufacturing the same

KR102964111B1KR 102964111 B1KR102964111 B1KR 102964111B1KR-102964111-B1

Abstract

A CMOS inverter according to one embodiment of the present invention may include an n-MOSFET and a p-MOSFET whose drain terminals are connected to each other, and a resistance region located at the drain terminals of the n-MOSFET and the p-MOSFET.

Inventors

  • 장지원
  • 임민수
  • 김준원
  • 이창욱

Assignees

  • 연세대학교 산학협력단

Dates

Publication Date
20260512
Application Date
20250825

Claims (20)

  1. n-MOSFET and p-MOSFET with drain terminals connected to each other; and A resistance region located at the drain terminals of the n-MOSFET and p-MOSFET; comprising, The above resistance region is, A device formed by controlling the doping concentration of the drain region of the n-MOSFET and p-MOSFET, characterized by having a lower doping concentration than that of the source region of the n-MOSFET and p-MOSFET. CMOS inverter.
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  4. In paragraph 1, The above source section is, Characterized by a doping concentration that is 10³ times the resistance region. CMOS inverter.
  5. In paragraph 1, The above n-MOSFET and p-MOSFET are, Characterized by the formation of a source layer through LDD (Lightly Doped Drain) and HDD (Highly Doped Drain) processes CMOS inverter.
  6. In paragraph 1, The source terminals of the n-MOSFET and p-MOSFET and the resistance region are, Characterized by being formed through epitaxial growth CMOS inverter.
  7. A method for manufacturing a CMOS inverter comprising an n-MOSFET and a p-MOSFET having drain terminals connected to each other, The step of forming the n-MOSFET and p-MOSFET such that a resistance region exists at the drain terminal; The step of forming the above n-MOSFET and p-MOSFET is Step of forming a substrate; A step of forming an oxide film on the above substrate; A step of forming a gate on the oxide film; A step of forming a source terminal having a first doping concentration on the substrate located in a first region adjacent to one end of the gate; and The step of forming the resistance region having a second doping concentration lower than the first doping concentration on the substrate located in a second region adjacent to the other end of the gate; CMOS inverter manufacturing method.
  8. In Paragraph 7, The above oxide film is, Characterized as being a gate oxide film CMOS inverter manufacturing method.
  9. In paragraph 8, The step of forming the above source section is, A step of masking the second region and performing LDD (Lightly Doped Drain) to dope the first region; A step of removing the gate oxide film of the first region and the second region; A step of forming a spacer in contact with the gate and the gate oxide film on the substrate of the first region and the second region; and The method comprises the step of forming the source section in the area of the first region where the spacer is not located. CMOS inverter manufacturing method.
  10. In Paragraph 9, The step of forming the source section in the area of the first region where the spacer is not located is: Characterized by masking the second region and performing HDD (Highly Doped Drain) to form the source stage. CMOS inverter manufacturing method.
  11. In Paragraph 10, The step of forming the resistance region above is, Characterized by masking the first region and doping the second region with the second doping concentration. CMOS inverter manufacturing method.
  12. In Paragraph 9, The step of forming the source section in the area of the first region where the spacer is not located is: Characterized by etching a portion of the substrate in the area of the first region where the spacer is not located, and forming the source end through epitaxial growth. CMOS inverter manufacturing method.
  13. In Paragraph 12, The step of forming the resistance region above is, Characterized by etching a portion of the substrate in the second region and forming the drain portion through epitaxial growth. CMOS inverter manufacturing method.
  14. In Paragraph 7, The above oxide film is, It is a screen oxide film, and The above gate is, Characterized by being a polygate CMOS inverter manufacturing method.
  15. In Paragraph 14, The step of forming the above source section is, A step of masking the second region and performing LDD (Lightly Doped Drain) to dope the first region; A step of removing the screen oxide film of the first and second regions; A step of forming a spacer in contact with the polygate and screen oxide film on the substrate of the first and second regions; The method comprises the step of forming the source section in the area of the first region where the spacer is not located. CMOS inverter manufacturing method.
  16. In paragraph 15, The step of forming the source section in the area of the first region where the spacer is not located is: Characterized by masking the second region and performing HDD (Highly Doped Drain) to form the source stage. CMOS inverter manufacturing method.
  17. In Paragraph 16, The step of forming the resistance region above is, Characterized by masking the first region and doping the second region with the second doping concentration. CMOS inverter manufacturing method.
  18. In paragraph 15, The step of forming the source section in the area of the first region where the spacer is not located is: Characterized by etching a portion of the substrate in the area of the first region where the spacer is not located, and forming the source end through epitaxial growth. CMOS inverter manufacturing method.
  19. In Paragraph 18, The step of forming the resistance region above is, Characterized by etching a portion of the substrate in the second region and forming the drain portion through epitaxial growth. CMOS inverter manufacturing method.
  20. In Paragraph 14, The step of forming the above n-MOSFET and p-MOSFET is A step of removing the screen oxide film located below the polygate and the polygate; A step of forming a dielectric layer on the region where the polygate was located on the substrate; and The method further comprises the step of forming a gate on the dielectric layer. CMOS inverter manufacturing method.

Description

CMOS inverter and method of manufacturing the same The present invention relates to a CMOS inverter and a method for manufacturing the same, and more specifically to a CMOS inverter structure that introduces a resistive region to implement ternary logic operation and a technology for manufacturing the same. A CMOS inverter is a fundamental logic element in digital circuits that performs the function of inverting the logic state of an input signal and outputting it when power is applied. Typically, a CMOS inverter has a structure in which one p-type metal-oxide semiconductor (p-MOSFET) and one n-type metal-oxide semiconductor (n-MOSFET) are connected in series; the input terminal is connected in common between the two transistors, and the output terminal is formed between the drains of the two transistors. Due to their low static power consumption and excellent switching characteristics, CMOS inverters have been widely adopted across high-speed digital circuits and integrated circuits (ICs). Recently, there has been increasing interest in multi-valued logic technology to improve the density of information storage and processing. Among these, ternary logic can have advantages over binary logic in terms of computational speed and energy efficiency. Accordingly, circuits with three stable output states based on CMOS inverter structures have been studied, and methods to implement ternary logic have been proposed by utilizing multiple power supply voltages or introducing dedicated level shifters and voltage divider circuits. However, these conventional technologies have limitations, such as complex circuit structures, the need for additional processes, issues with increased power consumption and area, and a lack of stability in intermediate voltage states. In particular, it is difficult to naturally implement intermediate voltage states based on existing CMOS processes, often requiring separate control circuits or multiple transistors. FIG. 1 is a circuit diagram of a CMOS inverter of the present invention according to one embodiment. Figure 2 is a transfer curve and VTC graph using an n-MOSFET and a p-MOSFET according to one embodiment. FIGS. 3 and 4 are graphs plotted vertically of the NET doping concentration of an n-MOSFET according to one embodiment, and FIGS. 5 and 6 are graphs plotted vertically of the NET doping concentration of a p-MOSFET according to one embodiment. FIG. 7 is a graph showing a transfer curve according to one embodiment. FIG. 8 is a flowchart relating to the steps of forming an n-MOSFET and a p-MOSFET according to one embodiment. FIG. 9 is a flowchart relating to the step of forming a source section according to one embodiment. FIGS. 10 and FIGS. 11 are schematic diagrams showing the process of forming an n-MOSFET and a p-MOSFET according to different embodiments. FIG. 12 is a flowchart relating to the steps of forming an n-MOSFET and a p-MOSFET according to another embodiment. FIG. 13 is a flowchart relating to the step (S240) of forming a source section according to one embodiment. FIGS. 14 and FIGS. 15 are schematic diagrams showing the process of forming n-MOSFET and p-MOSFET according to different embodiments. The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. The terms used in this specification will be briefly explained, and the invention will be described in detail. The terms used in this invention have been selected based on currently widely used general terms, taking into account their functions within the invention; however, these terms may vary depending on the intent of those skilled in the art, case law, the emergence of new technologies, etc. Additionally, in specific cases, terms have been arbitrarily selected by the applicant, and in such cases, their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this invention should be defined not merely by their names, but based on their meanings and the overall content of the invention. When a part of a specification is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Below, embodiments of the present invention are described in detail with reference to the attached drawings so that those skilled in the art can easily implement the invention. Additionally, parts of the drawings that are irrelevant to the description are o